Cache miss thread balancing

A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in th...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Christian Jacobi, Somin Song, Brian David Barrick, Gregory William Alexander, Anthony Saporito, Aaron Tsai, Thomas Winters Fox
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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