Cache retention data management

Cache retention data management

A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive ca...

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Hauptverfasser: Joseph Michael Pusdesris, Alex James Waugh, Dimitrios Kaseridis, Klas Magnus Bruce, Michael Alan Filippo, Jamshed Jalal
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Joseph Michael Pusdesris
Alex James Waugh
Dimitrios Kaseridis
Klas Magnus Bruce
Michael Alan Filippo
Jamshed Jalal
description A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_GB2566647B</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>GB2566647B</sourcerecordid><originalsourceid>FETCH-epo_espacenet_GB2566647B3</originalsourceid><addsrcrecordid>eNrjZJB3TkzOSFUoSi1JzSvJzM9TSEksSVTITcxLTE_NBQrxMLCmJeYUp_JCaW4GeTfXEGcP3dSC_PjU4oLE5NS81JJ4dycjUzMzMxNzJ2PCKgCNxiP_</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Cache retention data management</title><source>esp@cenet</source><creator>Joseph Michael Pusdesris ; Alex James Waugh ; Dimitrios Kaseridis ; Klas Magnus Bruce ; Michael Alan Filippo ; Jamshed Jalal</creator><creatorcontrib>Joseph Michael Pusdesris ; Alex James Waugh ; Dimitrios Kaseridis ; Klas Magnus Bruce ; Michael Alan Filippo ; Jamshed Jalal</creatorcontrib><description>A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20211027&amp;DB=EPODOC&amp;CC=GB&amp;NR=2566647B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20211027&amp;DB=EPODOC&amp;CC=GB&amp;NR=2566647B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Joseph Michael Pusdesris</creatorcontrib><creatorcontrib>Alex James Waugh</creatorcontrib><creatorcontrib>Dimitrios Kaseridis</creatorcontrib><creatorcontrib>Klas Magnus Bruce</creatorcontrib><creatorcontrib>Michael Alan Filippo</creatorcontrib><creatorcontrib>Jamshed Jalal</creatorcontrib><title>Cache retention data management</title><description>A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB3TkzOSFUoSi1JzSvJzM9TSEksSVTITcxLTE_NBQrxMLCmJeYUp_JCaW4GeTfXEGcP3dSC_PjU4oLE5NS81JJ4dycjUzMzMxNzJ2PCKgCNxiP_</recordid><startdate>20211027</startdate><enddate>20211027</enddate><creator>Joseph Michael Pusdesris</creator><creator>Alex James Waugh</creator><creator>Dimitrios Kaseridis</creator><creator>Klas Magnus Bruce</creator><creator>Michael Alan Filippo</creator><creator>Jamshed Jalal</creator><scope>EVB</scope></search><sort><creationdate>20211027</creationdate><title>Cache retention data management</title><author>Joseph Michael Pusdesris ; Alex James Waugh ; Dimitrios Kaseridis ; Klas Magnus Bruce ; Michael Alan Filippo ; Jamshed Jalal</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2566647B3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Joseph Michael Pusdesris</creatorcontrib><creatorcontrib>Alex James Waugh</creatorcontrib><creatorcontrib>Dimitrios Kaseridis</creatorcontrib><creatorcontrib>Klas Magnus Bruce</creatorcontrib><creatorcontrib>Michael Alan Filippo</creatorcontrib><creatorcontrib>Jamshed Jalal</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Joseph Michael Pusdesris</au><au>Alex James Waugh</au><au>Dimitrios Kaseridis</au><au>Klas Magnus Bruce</au><au>Michael Alan Filippo</au><au>Jamshed Jalal</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Cache retention data management</title><date>2021-10-27</date><risdate>2021</risdate><abstract>A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Cache retention data management
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T10%3A29%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Joseph%20Michael%20Pusdesris&rft.date=2021-10-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EGB2566647B%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true