An apparatus and method for controlling use of a register cache

An apparatus and method for controlling register cache prefetch. The apparatus has execution circuitry, a register file, and a register cache to cache a subset of the data values from the register file. Prefetch circuitry prefetches data values from the register file into the register cache. For each data value to be generated as a result of instructions being executed within the execution circuitry, timing indication storage holds a register address and timing information indicating when that data value will be generated 510. Cache usage control circuitry receives a plurality of register addresses associated with source data values for a pending instruction yet to be executed by the execution circuitry, to generate, with reference to the timing information, a timing control signal to control timing of at least one prefetch operation performed by the prefetch circuitry 515. When a pending instruction is dependent on the result from an earlier process, loading of the values relating to the pending instruction into the register cache may be deferred until the earlier process has completed.