Single ended bitline current sense amplifier for SRAM applications
Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a...
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| creator | Michael B Kugel Juergen Pille Alexander Fritsch Shankar Kalyanasundaram |
| description | Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_GB2558829B</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>GB2558829B</sourcerecordid><originalsourceid>FETCH-epo_espacenet_GB2558829B3</originalsourceid><addsrcrecordid>eNrjZHAKzsxLz0lVSM1LSU1RSMosycnMS1VILi0qSs0rUShOzStOVUjMLcjJTMtMLVJIyy9SCA5y9FVILAAKJSeWZObnFfMwsKYl5hSn8kJpbgZ5N9cQZw_d1IL8-NTigsTk1LzUknh3JyNTUwsLI0snY8IqAGHZMQk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Single ended bitline current sense amplifier for SRAM applications</title><source>esp@cenet</source><creator>Michael B Kugel ; Juergen Pille ; Alexander Fritsch ; Shankar Kalyanasundaram</creator><creatorcontrib>Michael B Kugel ; Juergen Pille ; Alexander Fritsch ; Shankar Kalyanasundaram</creatorcontrib><description>Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190306&DB=EPODOC&CC=GB&NR=2558829B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190306&DB=EPODOC&CC=GB&NR=2558829B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Michael B Kugel</creatorcontrib><creatorcontrib>Juergen Pille</creatorcontrib><creatorcontrib>Alexander Fritsch</creatorcontrib><creatorcontrib>Shankar Kalyanasundaram</creatorcontrib><title>Single ended bitline current sense amplifier for SRAM applications</title><description>Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAKzsxLz0lVSM1LSU1RSMosycnMS1VILi0qSs0rUShOzStOVUjMLcjJTMtMLVJIyy9SCA5y9FVILAAKJSeWZObnFfMwsKYl5hSn8kJpbgZ5N9cQZw_d1IL8-NTigsTk1LzUknh3JyNTUwsLI0snY8IqAGHZMQk</recordid><startdate>20190306</startdate><enddate>20190306</enddate><creator>Michael B Kugel</creator><creator>Juergen Pille</creator><creator>Alexander Fritsch</creator><creator>Shankar Kalyanasundaram</creator><scope>EVB</scope></search><sort><creationdate>20190306</creationdate><title>Single ended bitline current sense amplifier for SRAM applications</title><author>Michael B Kugel ; Juergen Pille ; Alexander Fritsch ; Shankar Kalyanasundaram</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2558829B3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Michael B Kugel</creatorcontrib><creatorcontrib>Juergen Pille</creatorcontrib><creatorcontrib>Alexander Fritsch</creatorcontrib><creatorcontrib>Shankar Kalyanasundaram</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Michael B Kugel</au><au>Juergen Pille</au><au>Alexander Fritsch</au><au>Shankar Kalyanasundaram</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Single ended bitline current sense amplifier for SRAM applications</title><date>2019-03-06</date><risdate>2019</risdate><abstract>Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Single ended bitline current sense amplifier for SRAM applications |
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