Design structure for reducing pre-charge voltage for static random-access memory arrays

A memory cell arrangement of SRAM cell groups may be provided in which in each of the groups multiple SRAM cells are connected to an input of a local read amplifier by at least one common local bit-line. Outputs of the amplifiers are connected to a shared global bit-line. The global bit-line is conn...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Rolf Sautter, Amira Rozenfeld, Alexander Fritsch, Dieter Wendel
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
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