Managing a power state of a processor

Managing a power state of a processor

A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle...

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Hauptverfasser: Devadatta V Bodas, Eric K. Mann
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Devadatta V Bodas
Eric K. Mann
description A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an interrupt is to be sent to the processor. The method also includes transitioning the processor from the deep idle state to the shallow idle state in response to receiving the signal and transitioning the processor from the shallow idle state to an active state in response to receiving the interrupt.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Managing a power state of a processor
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