Electronic circuit having serial latch scan chains
Disclosed is an electronic circuit 10 with latch scan chains 12, the circuit has a built-in test structure 14, generation means 16 that simultaneously generates scan-in data for each of the scan chains, and interception means 18 that intercepts test lines 20 of the scan chains. The test lines having...
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| creator | CEDRIC LICHTENAU JENS KUENZER TILMAN GLOEKLER ANDREAS KOENIG |
| description | Disclosed is an electronic circuit 10 with latch scan chains 12, the circuit has a built-in test structure 14, generation means 16 that simultaneously generates scan-in data for each of the scan chains, and interception means 18 that intercepts test lines 20 of the scan chains. The test lines having scan-in lines 22 and/or control lines 24. The interception means are responsive to the generation means in order to feed the generated scan-in data into each of the scan chains for initializing the electronic circuit. The test structure may input the scan-in data in parallel into the scan chains. The interception means may intercept the scan-in lines and the control lines, and the generation means may fetch pre-configured data from a memory for feeding into the scan-in lines. Also disclosed is a method of initialising the electronic circuit. |
| format | Patent |
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The test lines having scan-in lines 22 and/or control lines 24. The interception means are responsive to the generation means in order to feed the generated scan-in data into each of the scan chains for initializing the electronic circuit. The test structure may input the scan-in data in parallel into the scan chains. The interception means may intercept the scan-in lines and the control lines, and the generation means may fetch pre-configured data from a memory for feeding into the scan-in lines. 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Also disclosed is a method of initialising the electronic circuit.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDByzUlNLinKz8tMVkjOLEouzSxRyEgsy8xLVyhOLcpMzFHISSxJzlAoTk7MU0jOSMzMK-ZhYE1LzClO5YXS3Azybq4hzh66qQX58anFBYnJqXmpJfHuTkamhpbGppaOxoRVAAActCso</recordid><startdate>20150422</startdate><enddate>20150422</enddate><creator>CEDRIC LICHTENAU</creator><creator>JENS KUENZER</creator><creator>TILMAN GLOEKLER</creator><creator>ANDREAS KOENIG</creator><scope>EVB</scope></search><sort><creationdate>20150422</creationdate><title>Electronic circuit having serial latch scan chains</title><author>CEDRIC LICHTENAU ; JENS KUENZER ; TILMAN GLOEKLER ; ANDREAS KOENIG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2519359A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>CEDRIC LICHTENAU</creatorcontrib><creatorcontrib>JENS KUENZER</creatorcontrib><creatorcontrib>TILMAN GLOEKLER</creatorcontrib><creatorcontrib>ANDREAS KOENIG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CEDRIC LICHTENAU</au><au>JENS KUENZER</au><au>TILMAN GLOEKLER</au><au>ANDREAS KOENIG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Electronic circuit having serial latch scan chains</title><date>2015-04-22</date><risdate>2015</risdate><abstract>Disclosed is an electronic circuit 10 with latch scan chains 12, the circuit has a built-in test structure 14, generation means 16 that simultaneously generates scan-in data for each of the scan chains, and interception means 18 that intercepts test lines 20 of the scan chains. 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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS STATIC STORES TESTING |
| title | Electronic circuit having serial latch scan chains |
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