Simulation of integrated circuit design to accelerate memory walking sequences during simulations to verify microprocessor design

A system and method for saving time and cost during the design phase of a microprocessor integrated circuit component by computer simulation of a memory walking sequence. A simulation test-case is executed and one or more memory locations in the simulated memory are identified as eligible to contain valid data, it is then determined whether the identified eligible memory location is within a specified number of memory locations after a memory location to be processed by simulated hardware during the simulated memory walking sequence, if it is then the simulated hardware is allowed to process the memory location, otherwise the simulated hardware is advanced to a subsequent memory location, for example skipping memory locations that are known to be empty in the simulation, and is then allowed to process the subsequent memory location.