Bipolar transistor comprising a raised collector pedestal for reduced capacitance

A heterojunction bipolar transistor 100 and a method of forming the heterojunction bipolar transistor with a raised collector pedestal 125 in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal 125 is on the top surface of a substrate 121, 120, 101 and extends vertically through dielectric layer(s) 103, 104. The raised collector pedestal is un-doped or low-doped and is aligned above a sub-collector region 120, 121 contained within the substrate 101 and is narrower than that sub-collector region 120. An intrinsic base layer 105,132/131 is above the raised collector pedestal and the dielectric layer(s) 103, 104. An extrinsic base layer 141 is above the intrinsic base layer 132, 131. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently the base-collector junction capacitance is reduced and the maximum oscillation frequency (fmax) is increased.