Cache coherency between a CPU cache hierarchy and a graphics cache hierarchy

A processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. A graphics device 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The processor has a level 1...

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Hauptverfasser:	ARIEL BERKOVITS, OPER KAHN, ZEEV OFFEN, THOMAS PIAZZA, ALTUG KOKER, ROBERT L FARRELL
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	ARIEL BERKOVITS OPER KAHN ZEEV OFFEN THOMAS PIAZZA ALTUG KOKER ROBERT L FARRELL
description	A processor 101, such as a central processing unit (CPU), is in a cache coherency domain with a first set of coherency rules 109. A graphics device 105, such as a graphics processing unit (GPU), is in a different coherency domain 111 with a second set of coherency rules. The processor has a level 1 processor cache 103 (L1 cache) and a lower level processor cache 107. The graphics device has a level 1 graphics cache 104 (L1 cache) and a lower level graphics cache 108. Both the lower level caches use physical addresses. The central processing unit uses the first set of coherency rules with the lower level graphics cache. The graphics device uses the second set of coherency rules with the lower level graphics cache. The lower level graphics cache may be a mid-level or last level cache. The processor may snoop the lower level graphics cache.
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title	Cache coherency between a CPU cache hierarchy and a graphics cache hierarchy
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