Parallel processing system using dual port memories to communicate between each processor and the public memory bus

Parallel processing system using dual port memories to communicate between each processor and the public memory bus

A parallel processing system 13 has a number of processing elements 16 connected to a public memory bus 18 via multiple port memories 10. One port of each memory is connected to the bus. The other ports are connected to processors. The multiple port memory is configured as a shared memory resource,...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MICHAEL DOYLE, BRENNAN ROSS, MICHAEL MANZKE
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MICHAEL DOYLE
BRENNAN ROSS
MICHAEL MANZKE
description A parallel processing system 13 has a number of processing elements 16 connected to a public memory bus 18 via multiple port memories 10. One port of each memory is connected to the bus. The other ports are connected to processors. The multiple port memory is configured as a shared memory resource, which can be accessed both by the processors connected to the ports of the memory and by processors connected to the public memory bus. The memory may be divided into segments based on the data path width and the size of the memory. The system may comprise a number of separate nodes 11, 12, each of which has a number of processing elements and a number of multiple port memories.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_GB2483884A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>GB2483884A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_GB2483884A3</originalsourceid><addsrcrecordid>eNqFjDsOwjAQRNNQIOAM7AVoIEVaQHxKCvpo4wzEku21vLZQbg_iU1ONRm_eTCu9cGLn4CgmMVC14U46aoan8i594ReUlMnDS7JQykJGvC_BGs6gDvkBBAKb4XcjiTj0lAdQLJ2z5mOP1BWdV5MbO8Xim7NqeTxc9-cVorTQyAYBuT3t1nWzaZp6u_m_eAKTg0Q6</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Parallel processing system using dual port memories to communicate between each processor and the public memory bus</title><source>esp@cenet</source><creator>MICHAEL DOYLE ; BRENNAN ROSS ; MICHAEL MANZKE</creator><creatorcontrib>MICHAEL DOYLE ; BRENNAN ROSS ; MICHAEL MANZKE</creatorcontrib><description>A parallel processing system 13 has a number of processing elements 16 connected to a public memory bus 18 via multiple port memories 10. One port of each memory is connected to the bus. The other ports are connected to processors. The multiple port memory is configured as a shared memory resource, which can be accessed both by the processors connected to the ports of the memory and by processors connected to the public memory bus. The memory may be divided into segments based on the data path width and the size of the memory. The system may comprise a number of separate nodes 11, 12, each of which has a number of processing elements and a number of multiple port memories.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120328&amp;DB=EPODOC&amp;CC=GB&amp;NR=2483884A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120328&amp;DB=EPODOC&amp;CC=GB&amp;NR=2483884A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MICHAEL DOYLE</creatorcontrib><creatorcontrib>BRENNAN ROSS</creatorcontrib><creatorcontrib>MICHAEL MANZKE</creatorcontrib><title>Parallel processing system using dual port memories to communicate between each processor and the public memory bus</title><description>A parallel processing system 13 has a number of processing elements 16 connected to a public memory bus 18 via multiple port memories 10. One port of each memory is connected to the bus. The other ports are connected to processors. The multiple port memory is configured as a shared memory resource, which can be accessed both by the processors connected to the ports of the memory and by processors connected to the public memory bus. The memory may be divided into segments based on the data path width and the size of the memory. The system may comprise a number of separate nodes 11, 12, each of which has a number of processing elements and a number of multiple port memories.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFjDsOwjAQRNNQIOAM7AVoIEVaQHxKCvpo4wzEku21vLZQbg_iU1ONRm_eTCu9cGLn4CgmMVC14U46aoan8i594ReUlMnDS7JQykJGvC_BGs6gDvkBBAKb4XcjiTj0lAdQLJ2z5mOP1BWdV5MbO8Xim7NqeTxc9-cVorTQyAYBuT3t1nWzaZp6u_m_eAKTg0Q6</recordid><startdate>20120328</startdate><enddate>20120328</enddate><creator>MICHAEL DOYLE</creator><creator>BRENNAN ROSS</creator><creator>MICHAEL MANZKE</creator><scope>EVB</scope></search><sort><creationdate>20120328</creationdate><title>Parallel processing system using dual port memories to communicate between each processor and the public memory bus</title><author>MICHAEL DOYLE ; BRENNAN ROSS ; MICHAEL MANZKE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2483884A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MICHAEL DOYLE</creatorcontrib><creatorcontrib>BRENNAN ROSS</creatorcontrib><creatorcontrib>MICHAEL MANZKE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MICHAEL DOYLE</au><au>BRENNAN ROSS</au><au>MICHAEL MANZKE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Parallel processing system using dual port memories to communicate between each processor and the public memory bus</title><date>2012-03-28</date><risdate>2012</risdate><abstract>A parallel processing system 13 has a number of processing elements 16 connected to a public memory bus 18 via multiple port memories 10. One port of each memory is connected to the bus. The other ports are connected to processors. The multiple port memory is configured as a shared memory resource, which can be accessed both by the processors connected to the ports of the memory and by processors connected to the public memory bus. The memory may be divided into segments based on the data path width and the size of the memory. The system may comprise a number of separate nodes 11, 12, each of which has a number of processing elements and a number of multiple port memories.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_GB2483884A
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Parallel processing system using dual port memories to communicate between each processor and the public memory bus
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T22%3A40%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MICHAEL%20DOYLE&rft.date=2012-03-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EGB2483884A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true