Instruction for enabling a processor wait state
In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The proces...
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| creator | Per Hammarlund Scott D. Rodgers Taraneh Bahrami Prashant Sethi Stephen H Gunther Martin G Dixon |
| description | In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed. |
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Rodgers ; Taraneh Bahrami ; Prashant Sethi ; Stephen H Gunther ; Martin G Dixon</creatorcontrib><description>In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171018&DB=EPODOC&CC=GB&NR=2483012B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171018&DB=EPODOC&CC=GB&NR=2483012B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Per Hammarlund</creatorcontrib><creatorcontrib>Scott D. Rodgers</creatorcontrib><creatorcontrib>Taraneh Bahrami</creatorcontrib><creatorcontrib>Prashant Sethi</creatorcontrib><creatorcontrib>Stephen H Gunther</creatorcontrib><creatorcontrib>Martin G Dixon</creatorcontrib><title>Instruction for enabling a processor wait state</title><description>In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND3zCsuKSpNLsnMz1NIyy9SSM1LTMrJzEtXSFQoKMpPTi0uBgqWJ2aWKBSXJJak8jCwpiXmFKfyQmluBnk31xBnD93Ugvz41OKCxOTUvNSSeHcnIxMLYwNDIydjwioAnDAqLA</recordid><startdate>20171018</startdate><enddate>20171018</enddate><creator>Per Hammarlund</creator><creator>Scott D. Rodgers</creator><creator>Taraneh Bahrami</creator><creator>Prashant Sethi</creator><creator>Stephen H Gunther</creator><creator>Martin G Dixon</creator><scope>EVB</scope></search><sort><creationdate>20171018</creationdate><title>Instruction for enabling a processor wait state</title><author>Per Hammarlund ; Scott D. Rodgers ; Taraneh Bahrami ; Prashant Sethi ; Stephen H Gunther ; Martin G Dixon</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2483012B3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2017</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Per Hammarlund</creatorcontrib><creatorcontrib>Scott D. Rodgers</creatorcontrib><creatorcontrib>Taraneh Bahrami</creatorcontrib><creatorcontrib>Prashant Sethi</creatorcontrib><creatorcontrib>Stephen H Gunther</creatorcontrib><creatorcontrib>Martin G Dixon</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Per Hammarlund</au><au>Scott D. Rodgers</au><au>Taraneh Bahrami</au><au>Prashant Sethi</au><au>Stephen H Gunther</au><au>Martin G Dixon</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Instruction for enabling a processor wait state</title><date>2017-10-18</date><risdate>2017</risdate><abstract>In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Instruction for enabling a processor wait state |
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