Instruction for enabling a processor wait state

In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The proces...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Per Hammarlund, Scott D. Rodgers, Taraneh Bahrami, Prashant Sethi, Stephen H Gunther, Martin G Dixon
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.