Method and system for verification of microprocessor designs with multiple power gate domains

The invention relates to a method and a system for verifying a microprocessor design with multiple power gate domains (21, 22). The checks are done via structural checks of a hierarchical netlist of the design and use signal based traversion. Specifically, the invention encompasses an identification...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	JUERGEN WAKUNDA, HARRY BAROWSKI, CHRISTOPH JAESCHKE, TIM NIGGEMEIER
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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