Translating subject code with floating point operations to target code according to the precision required by the floating point operation

A computing system 10 capable of handling floating point operations during program code conversion is described, comprising a processor 13 including a floating point unit 14 and an integer unit 16. The computing system further comprises a translator unit 19 arranged to receive subject code instructions 17 including at least one instruction relating to a floating point operation and in response to generate corresponding target code 21 for execution on said processor. To handle floating point operations a floating point status unit 195 and a floating point control unit 196 are provided within the translator. These units are cause the translator unit to generate either: target code for performing the floating point operations directly on the floating point unit; or target code for performing the floating point operations indirectly, for example using a combination of the integer unit and the floating point unit. The translation may be based upon a determination of the precision actually required by the floating point operation. The translator may perform emulation of a subject processor instruction set architecture (ISA) having one floating point precision on a target processor ISA with a different (or the same) floating point precision or optimization of subject code to create optimised target code for the same processor ISA.