Memory cell structure having nitride layer with reduced charge loss and method for fabricating same

According to one embodiment, a memory cell structure comprises a semiconductor substrate (210), a first silicon oxide layer (215) situated over the semiconductor substrate, a charge storing layer (220) situated over the first silicon oxide layer, a second silicon oxide layer (225) situated over the...

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Hauptverfasser:	MARK T RAMSBEY, ROBERT BERTRAM OGLE JR, ROBERT B CLARK-PHELPS, ARVIND HALLIYAL, KUO-TUNG CHANG, GEORGE JONATHAN KLUTH, WENMEI LI, JOONG S JEON, HUICAI ZHONG
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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