Memory cell structure having nitride layer with reduced charge loss and method for fabricating same
According to one embodiment, a memory cell structure comprises a semiconductor substrate (210), a first silicon oxide layer (215) situated over the semiconductor substrate, a charge storing layer (220) situated over the first silicon oxide layer, a second silicon oxide layer (225) situated over the...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | MARK T RAMSBEY ROBERT BERTRAM OGLE JR ROBERT B CLARK-PHELPS ARVIND HALLIYAL KUO-TUNG CHANG GEORGE JONATHAN KLUTH WENMEI LI JOONG S JEON HUICAI ZHONG |
| description | According to one embodiment, a memory cell structure comprises a semiconductor substrate (210), a first silicon oxide layer (215) situated over the semiconductor substrate, a charge storing layer (220) situated over the first silicon oxide layer, a second silicon oxide layer (225) situated over the charge storing layer, and a gate layer (230) situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer (220) comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer (220). The reduced charge loss in the charge storing layer (220) has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_GB2420226A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>GB2420226A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_GB2420226A3</originalsourceid><addsrcrecordid>eNqFjL0KAjEQBq-xEPUZ3BcQJIq9ij-Nnf2xJt9dArnk2Owp9_Yq2FtNMcNMK3tDl2UkixipqAxWBwF5fobUUgoqwYEijxB6BfUkcIOFI-tZ2o_JpRAnRx3UZ0dNFmr4IcGyfg-FO8yrScOxYPHjrFqeT_fjdYU-1yg9WyRofTmYrVkbs9tv_hdvtxw9iw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Memory cell structure having nitride layer with reduced charge loss and method for fabricating same</title><source>esp@cenet</source><creator>MARK T RAMSBEY ; ROBERT BERTRAM OGLE JR ; ROBERT B CLARK-PHELPS ; ARVIND HALLIYAL ; KUO-TUNG CHANG ; GEORGE JONATHAN KLUTH ; WENMEI LI ; JOONG S JEON ; HUICAI ZHONG</creator><creatorcontrib>MARK T RAMSBEY ; ROBERT BERTRAM OGLE JR ; ROBERT B CLARK-PHELPS ; ARVIND HALLIYAL ; KUO-TUNG CHANG ; GEORGE JONATHAN KLUTH ; WENMEI LI ; JOONG S JEON ; HUICAI ZHONG</creatorcontrib><description>According to one embodiment, a memory cell structure comprises a semiconductor substrate (210), a first silicon oxide layer (215) situated over the semiconductor substrate, a charge storing layer (220) situated over the first silicon oxide layer, a second silicon oxide layer (225) situated over the charge storing layer, and a gate layer (230) situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer (220) comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer (220). The reduced charge loss in the charge storing layer (220) has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060517&DB=EPODOC&CC=GB&NR=2420226A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060517&DB=EPODOC&CC=GB&NR=2420226A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MARK T RAMSBEY</creatorcontrib><creatorcontrib>ROBERT BERTRAM OGLE JR</creatorcontrib><creatorcontrib>ROBERT B CLARK-PHELPS</creatorcontrib><creatorcontrib>ARVIND HALLIYAL</creatorcontrib><creatorcontrib>KUO-TUNG CHANG</creatorcontrib><creatorcontrib>GEORGE JONATHAN KLUTH</creatorcontrib><creatorcontrib>WENMEI LI</creatorcontrib><creatorcontrib>JOONG S JEON</creatorcontrib><creatorcontrib>HUICAI ZHONG</creatorcontrib><title>Memory cell structure having nitride layer with reduced charge loss and method for fabricating same</title><description>According to one embodiment, a memory cell structure comprises a semiconductor substrate (210), a first silicon oxide layer (215) situated over the semiconductor substrate, a charge storing layer (220) situated over the first silicon oxide layer, a second silicon oxide layer (225) situated over the charge storing layer, and a gate layer (230) situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer (220) comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer (220). The reduced charge loss in the charge storing layer (220) has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFjL0KAjEQBq-xEPUZ3BcQJIq9ij-Nnf2xJt9dArnk2Owp9_Yq2FtNMcNMK3tDl2UkixipqAxWBwF5fobUUgoqwYEijxB6BfUkcIOFI-tZ2o_JpRAnRx3UZ0dNFmr4IcGyfg-FO8yrScOxYPHjrFqeT_fjdYU-1yg9WyRofTmYrVkbs9tv_hdvtxw9iw</recordid><startdate>20060517</startdate><enddate>20060517</enddate><creator>MARK T RAMSBEY</creator><creator>ROBERT BERTRAM OGLE JR</creator><creator>ROBERT B CLARK-PHELPS</creator><creator>ARVIND HALLIYAL</creator><creator>KUO-TUNG CHANG</creator><creator>GEORGE JONATHAN KLUTH</creator><creator>WENMEI LI</creator><creator>JOONG S JEON</creator><creator>HUICAI ZHONG</creator><scope>EVB</scope></search><sort><creationdate>20060517</creationdate><title>Memory cell structure having nitride layer with reduced charge loss and method for fabricating same</title><author>MARK T RAMSBEY ; ROBERT BERTRAM OGLE JR ; ROBERT B CLARK-PHELPS ; ARVIND HALLIYAL ; KUO-TUNG CHANG ; GEORGE JONATHAN KLUTH ; WENMEI LI ; JOONG S JEON ; HUICAI ZHONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2420226A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MARK T RAMSBEY</creatorcontrib><creatorcontrib>ROBERT BERTRAM OGLE JR</creatorcontrib><creatorcontrib>ROBERT B CLARK-PHELPS</creatorcontrib><creatorcontrib>ARVIND HALLIYAL</creatorcontrib><creatorcontrib>KUO-TUNG CHANG</creatorcontrib><creatorcontrib>GEORGE JONATHAN KLUTH</creatorcontrib><creatorcontrib>WENMEI LI</creatorcontrib><creatorcontrib>JOONG S JEON</creatorcontrib><creatorcontrib>HUICAI ZHONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MARK T RAMSBEY</au><au>ROBERT BERTRAM OGLE JR</au><au>ROBERT B CLARK-PHELPS</au><au>ARVIND HALLIYAL</au><au>KUO-TUNG CHANG</au><au>GEORGE JONATHAN KLUTH</au><au>WENMEI LI</au><au>JOONG S JEON</au><au>HUICAI ZHONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory cell structure having nitride layer with reduced charge loss and method for fabricating same</title><date>2006-05-17</date><risdate>2006</risdate><abstract>According to one embodiment, a memory cell structure comprises a semiconductor substrate (210), a first silicon oxide layer (215) situated over the semiconductor substrate, a charge storing layer (220) situated over the first silicon oxide layer, a second silicon oxide layer (225) situated over the charge storing layer, and a gate layer (230) situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer (220) comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer (220). The reduced charge loss in the charge storing layer (220) has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_GB2420226A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Memory cell structure having nitride layer with reduced charge loss and method for fabricating same |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T09%3A07%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MARK%20T%20RAMSBEY&rft.date=2006-05-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EGB2420226A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |