Logic circuit

A reconfigurable multiplier array is constructed using an array of 4 bit Flexible Array Blocks (FABs). The array can be configured to perform a number of 4n x 4m bit binary multiplications. Each multiplier can be configured to perform either unsigned, or two's complement binary multiplication.

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Hauptverfasser:	SIMON DOMINIC HAYNES, PETER YING KAY CHEUNG
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
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creator	SIMON DOMINIC HAYNES PETER YING KAY CHEUNG
description	A reconfigurable multiplier array is constructed using an array of 4 bit Flexible Array Blocks (FABs). The array can be configured to perform a number of 4n x 4m bit binary multiplications. Each multiplier can be configured to perform either unsigned, or two's complement binary multiplication.
format	Patent
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subjects	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
title	Logic circuit
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