Method of forming a buried plate of a trench capacitor
A trench 104 is etched in a silicon wafer 100 and an arsenic doped glass layer 106 is formed in the trench. A second layer 108 of undoped glass is then deposited on the layer 106. After filling the trench with photoresist and partially removing the photoresist, the unprotected portions of the layers...
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creator | PAUL WENSLEY GUENTHER KOFFLER |
description | A trench 104 is etched in a silicon wafer 100 and an arsenic doped glass layer 106 is formed in the trench. A second layer 108 of undoped glass is then deposited on the layer 106. After filling the trench with photoresist and partially removing the photoresist, the unprotected portions of the layers 106,108 are wet etched. The remaining photoresist is then removed and the device is annealed to out-diffuse arsenic from the layer 106 thereby forming an arsenic doped region 114 which constitutes a buried plate of the capacitor. The layers 106,108 are then etched away using hydrofluoric acid. |
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After filling the trench with photoresist and partially removing the photoresist, the unprotected portions of the layers 106,108 are wet etched. The remaining photoresist is then removed and the device is annealed to out-diffuse arsenic from the layer 106 thereby forming an arsenic doped region 114 which constitutes a buried plate of the capacitor. The layers 106,108 are then etched away using hydrofluoric acid.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2000</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000531&DB=EPODOC&CC=GB&NR=2344215A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20000531&DB=EPODOC&CC=GB&NR=2344215A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PAUL WENSLEY</creatorcontrib><creatorcontrib>GUENTHER KOFFLER</creatorcontrib><title>Method of forming a buried plate of a trench capacitor</title><description>A trench 104 is etched in a silicon wafer 100 and an arsenic doped glass layer 106 is formed in the trench. A second layer 108 of undoped glass is then deposited on the layer 106. After filling the trench with photoresist and partially removing the photoresist, the unprotected portions of the layers 106,108 are wet etched. The remaining photoresist is then removed and the device is annealed to out-diffuse arsenic from the layer 106 thereby forming an arsenic doped region 114 which constitutes a buried plate of the capacitor. The layers 106,108 are then etched away using hydrofluoric acid.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2000</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDzTS3JyE9RyE9TSMsvys3MS1dIVEgqLcpMTVEoyEksSQXJJCqUFKXmJWcoJCcWJCZnluQX8TCwpiXmFKfyQmluBnk31xBnD93Ugvz41GKgqtS81JJ4dycjYxMTI0NTR2PCKgCRzyvd</recordid><startdate>20000531</startdate><enddate>20000531</enddate><creator>PAUL WENSLEY</creator><creator>GUENTHER KOFFLER</creator><scope>EVB</scope></search><sort><creationdate>20000531</creationdate><title>Method of forming a buried plate of a trench capacitor</title><author>PAUL WENSLEY ; GUENTHER KOFFLER</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2344215A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2000</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>PAUL WENSLEY</creatorcontrib><creatorcontrib>GUENTHER KOFFLER</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PAUL WENSLEY</au><au>GUENTHER KOFFLER</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of forming a buried plate of a trench capacitor</title><date>2000-05-31</date><risdate>2000</risdate><abstract>A trench 104 is etched in a silicon wafer 100 and an arsenic doped glass layer 106 is formed in the trench. A second layer 108 of undoped glass is then deposited on the layer 106. After filling the trench with photoresist and partially removing the photoresist, the unprotected portions of the layers 106,108 are wet etched. The remaining photoresist is then removed and the device is annealed to out-diffuse arsenic from the layer 106 thereby forming an arsenic doped region 114 which constitutes a buried plate of the capacitor. The layers 106,108 are then etched away using hydrofluoric acid.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Method of forming a buried plate of a trench capacitor |
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