CONTROL CHANNEL INTERFACE CIRCUIT
There is disclosed a control channel interface circuit for interfacing a port processor of a distributed multiprocessor communication system to a common time division multiplexed bus. The detection, extraction and synchronization of control messages passed between a central processor and port proces...
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| creator | MARK JEFFREY KOENIG KEVIN JYO OYE |
| description | There is disclosed a control channel interface circuit for interfacing a port processor of a distributed multiprocessor communication system to a common time division multiplexed bus. The detection, extraction and synchronization of control messages passed between a central processor and port processor via a TDM bus are handled by the interface unit thereby relieving a port processor of this burden. A group of control time slots within a system frame are dedicated for the transfer of control messages between port processors and a central processor. The interface unit also monitors the operability of a respective port processor and automatically disables a faulty processor. |
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The detection, extraction and synchronization of control messages passed between a central processor and port processor via a TDM bus are handled by the interface unit thereby relieving a port processor of this burden. A group of control time slots within a system frame are dedicated for the transfer of control messages between port processors and a central processor. The interface unit also monitors the operability of a respective port processor and automatically disables a faulty processor.</description><edition>4</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; SELECTING</subject><creationdate>1985</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19850619&DB=EPODOC&CC=GB&NR=2149999A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19850619&DB=EPODOC&CC=GB&NR=2149999A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MARK JEFFREY KOENIG</creatorcontrib><creatorcontrib>KEVIN JYO OYE</creatorcontrib><title>CONTROL CHANNEL INTERFACE CIRCUIT</title><description>There is disclosed a control channel interface circuit for interfacing a port processor of a distributed multiprocessor communication system to a common time division multiplexed bus. The detection, extraction and synchronization of control messages passed between a central processor and port processor via a TDM bus are handled by the interface unit thereby relieving a port processor of this burden. A group of control time slots within a system frame are dedicated for the transfer of control messages between port processors and a central processor. The interface unit also monitors the operability of a respective port processor and automatically disables a faulty processor.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SELECTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1985</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFB09vcLCfL3UXD2cPTzc_VR8PQLcQ1yc3R2VXD2DHIO9QzhYWBNS8wpTuWF0twM8m6uIc4euqkF-fGpxQWJyal5qSXx7k5GhiaWQOBoTFgFAJUDIWg</recordid><startdate>19850619</startdate><enddate>19850619</enddate><creator>MARK JEFFREY KOENIG</creator><creator>KEVIN JYO OYE</creator><scope>EVB</scope></search><sort><creationdate>19850619</creationdate><title>CONTROL CHANNEL INTERFACE CIRCUIT</title><author>MARK JEFFREY KOENIG ; KEVIN JYO OYE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB2149999A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1985</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SELECTING</topic><toplevel>online_resources</toplevel><creatorcontrib>MARK JEFFREY KOENIG</creatorcontrib><creatorcontrib>KEVIN JYO OYE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MARK JEFFREY KOENIG</au><au>KEVIN JYO OYE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CONTROL CHANNEL INTERFACE CIRCUIT</title><date>1985-06-19</date><risdate>1985</risdate><abstract>There is disclosed a control channel interface circuit for interfacing a port processor of a distributed multiprocessor communication system to a common time division multiplexed bus. The detection, extraction and synchronization of control messages passed between a central processor and port processor via a TDM bus are handled by the interface unit thereby relieving a port processor of this burden. A group of control time slots within a system frame are dedicated for the transfer of control messages between port processors and a central processor. The interface unit also monitors the operability of a respective port processor and automatically disables a faulty processor.</abstract><edition>4</edition><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS SELECTING |
| title | CONTROL CHANNEL INTERFACE CIRCUIT |
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