SEMICONDUCTOR DEVICE FOR A TRIGGER STORAGE CELL

1298053 Semi-conductor devices J N DYAKOV V Y KREMLEV V N STRUKOV and D O CHUTUEV 26 March 1971 7884/71 Heading H1K The invention relates to a multi-emitter transistor for use (as shown) with a like device to form a memory cell suitable for use in a storage matrix. The two transistors 1, 2 shown are formed in an N-type epitaxial layer carried by a P-type silicon substrate and are mutually isolated by a P-type diffused wall. Each has an "information" emitter 12, 16 (and may have several), an "address" emitter 11, 15, and a base contact 10, 14. The bases are each crosscoupled with a collector contact 17, 13, and power is supplied to a line linking second collector contacts 6, 7 of the transistors. The relative placing of the collectors and various emitters within each transistor is such that the normally required collector resistor is formed by that part of the epitaxial layer between the two collector contacts and is such that that part of the collector base junction beneath the "information" emitter is maintained under reverse bias at all times in operation to prevent the "information" emitter functioning as a spurious collector.