SIMULATION OF CYBERNETIC LEARNING

1281513 Learning systems NATIONAL RESEARCH DEVELOPMENT CORP 29 Sept 1969 [27 June 1968] 30657/68 Heading G4R A plurality of different electrical event signals are generated containing linking signals capable of establishing an association between associated events, the linking signals being recorded, reproduced and then compared with a reoccurring event signal to identify the linking signal or signals pertaining both to this reoccurring event and to a formerly associated event, an output signal pertaining to the associated event being generated. In Fig. 2, master (clock) pulses from a master track of a circulating magnetic tape loop (or drum) 110 drive a multi-decade counter 141, 142, 143, each decade having 10 outputs (not all shown). The units and tens outputs are combined in pairs with respective secondary event signals from switches at 144 to provide pulses at respective times from OR 145 for any of 100 possible secondary events. If one of 10 possible primary events occurs, a corresponding switch 146 passes a respective hundreds output from the counter via OR 147 to be ANDed 150 with the output of OR 145 to provide a selectively timed linking signal which is recorded on a memory track of tape 110. A reoccurring secondary event produces a pulse from OR 145 which is compared in AND 158 with the linking signals read from the memory track, to produce an output in an output channel 153 selected by the currently-active hundreds output of the counter at ANDs 155. Such an output is also produced by a primary event via the direct connection shown from OR 147 to OR 157. Randomly varying time delays may be inserted preceding or following OR 145. Forgetting can be simulated by randomly positioned erasing pulses applied to the memory track. The primary and secondary events may be operations of a machine tool and recognition of particular spoken words respectively. An integrating or staircase circuit may be used in each output channel to require a predetermined number of activations before an output is produced. In another embodiment, the master pulses are frequency-divided by different prime numbers by respective counters, the counter outputs (one per counter) going via respective event switches to a two-or-more detector which provides the linking signals which are recorded on the memory track. The detector inputs are also ORed and applied to an AND which compares them with the linking signals read from the memory track, an output from the AND pulsing an output cha