DATA PROCESSING SYSTEM
1,243,619. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 14 May, 1970 [27 June, 1969], No. 23367/70. Heading G4A. A data processing system comprises a CPU connected (e.g. by a ring bus) to a plurality of ancillary units (e.g. I/O control units or other CPU's), each of which includes me...
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| creator | LEOPOLD REICHL REINHARD HARTWICH HORST VON DER HEYDEN HANS HERMANN LAMPE |
| description | 1,243,619. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 14 May, 1970 [27 June, 1969], No. 23367/70. Heading G4A. A data processing system comprises a CPU connected (e.g. by a ring bus) to a plurality of ancillary units (e.g. I/O control units or other CPU's), each of which includes means to generate a unit selected signal when it correctly or falsely responds to an address signal received from the CPU, there being means to generate a warning signal if two or more of the ancillary units generate unit selected signals in response to the same address signal. A unit selected signal is generated if an address bus portion of the ring bus has the address of the unit on it and at least one bit on a data bus portion of the ring bus is 1. The unit selected signal is ORed on to a line of the ring bus, and if the incoming portion of this line at any unit producing a unit selected signal already has such a signal on it, a warning signal is ORed on to another line of the ring bus. The CPU responds to the warning signal causing each unit producing a unit selected signal to identify itself to the CPU by a signal on a respective line. |
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A data processing system comprises a CPU connected (e.g. by a ring bus) to a plurality of ancillary units (e.g. I/O control units or other CPU's), each of which includes means to generate a unit selected signal when it correctly or falsely responds to an address signal received from the CPU, there being means to generate a warning signal if two or more of the ancillary units generate unit selected signals in response to the same address signal. A unit selected signal is generated if an address bus portion of the ring bus has the address of the unit on it and at least one bit on a data bus portion of the ring bus is 1. The unit selected signal is ORed on to a line of the ring bus, and if the incoming portion of this line at any unit producing a unit selected signal already has such a signal on it, a warning signal is ORed on to another line of the ring bus. The CPU responds to the warning signal causing each unit producing a unit selected signal to identify itself to the CPU by a signal on a respective line.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1971</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19710825&DB=EPODOC&CC=GB&NR=1243619A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19710825&DB=EPODOC&CC=GB&NR=1243619A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEOPOLD REICHL</creatorcontrib><creatorcontrib>REINHARD HARTWICH</creatorcontrib><creatorcontrib>HORST VON DER HEYDEN</creatorcontrib><creatorcontrib>HANS HERMANN LAMPE</creatorcontrib><title>DATA PROCESSING SYSTEM</title><description>1,243,619. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 14 May, 1970 [27 June, 1969], No. 23367/70. Heading G4A. A data processing system comprises a CPU connected (e.g. by a ring bus) to a plurality of ancillary units (e.g. I/O control units or other CPU's), each of which includes means to generate a unit selected signal when it correctly or falsely responds to an address signal received from the CPU, there being means to generate a warning signal if two or more of the ancillary units generate unit selected signals in response to the same address signal. A unit selected signal is generated if an address bus portion of the ring bus has the address of the unit on it and at least one bit on a data bus portion of the ring bus is 1. The unit selected signal is ORed on to a line of the ring bus, and if the incoming portion of this line at any unit producing a unit selected signal already has such a signal on it, a warning signal is ORed on to another line of the ring bus. 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Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 14 May, 1970 [27 June, 1969], No. 23367/70. Heading G4A. A data processing system comprises a CPU connected (e.g. by a ring bus) to a plurality of ancillary units (e.g. I/O control units or other CPU's), each of which includes means to generate a unit selected signal when it correctly or falsely responds to an address signal received from the CPU, there being means to generate a warning signal if two or more of the ancillary units generate unit selected signals in response to the same address signal. A unit selected signal is generated if an address bus portion of the ring bus has the address of the unit on it and at least one bit on a data bus portion of the ring bus is 1. The unit selected signal is ORed on to a line of the ring bus, and if the incoming portion of this line at any unit producing a unit selected signal already has such a signal on it, a warning signal is ORed on to another line of the ring bus. The CPU responds to the warning signal causing each unit producing a unit selected signal to identify itself to the CPU by a signal on a respective line.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | DATA PROCESSING SYSTEM |
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