IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS
1,243,160. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 8 May, 1970 [30 May, 1969], No. 22256/70. Heading G4A. A data processing system includes a CPU, ancillary (e.g. I/O) units connected thereto by a ring bus system comprising an address bus and a data bus, and switching means selectivel...
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creator | LEOPOLD REICHL HERMANN WEBER ROBERT VACHENAUER FRITZ KOEDERITZ HELMUT PAINKE HANS HERMANN LAMPE EDWIN VOGT GUNTER KNAUFT |
description | 1,243,160. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 8 May, 1970 [30 May, 1969], No. 22256/70. Heading G4A. A data processing system includes a CPU, ancillary (e.g. I/O) units connected thereto by a ring bus system comprising an address bus and a data bus, and switching means selectively operable in response to a signal indicative of the absence of execution of a programme instruction involving communication between the CPU and the ancillary units, to apply an address of an ancillary unit defined by manually settable test means to the address bus, the addressed unit supplying data via the data bus to the CPU. The switching means only operates in response to the signal in this way if a manual mode switch is set to "I/O display", the data sent to the CPU being sense data which is displayed on lamps on the CPU control panel. If the mode switch is set to "I/O status stop", then in the presence of the "signal" mentioned above, the machine stops (i.e. at the address defined by the manually settable test means) when the contents of the data bus equal the setting of further manual switches. When test and maintenance work as above is not being performed, the manually settable test means and the further manual switches are used as conventional address and data configuration switches, and the lamps are used for displaying register and storage contents. |
format | Patent |
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Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 8 May, 1970 [30 May, 1969], No. 22256/70. Heading G4A. A data processing system includes a CPU, ancillary (e.g. I/O) units connected thereto by a ring bus system comprising an address bus and a data bus, and switching means selectively operable in response to a signal indicative of the absence of execution of a programme instruction involving communication between the CPU and the ancillary units, to apply an address of an ancillary unit defined by manually settable test means to the address bus, the addressed unit supplying data via the data bus to the CPU. The switching means only operates in response to the signal in this way if a manual mode switch is set to "I/O display", the data sent to the CPU being sense data which is displayed on lamps on the CPU control panel. If the mode switch is set to "I/O status stop", then in the presence of the "signal" mentioned above, the machine stops (i.e. at the address defined by the manually settable test means) when the contents of the data bus equal the setting of further manual switches. When test and maintenance work as above is not being performed, the manually settable test means and the further manual switches are used as conventional address and data configuration switches, and the lamps are used for displaying register and storage contents.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1971</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19710818&DB=EPODOC&CC=GB&NR=1243160A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19710818&DB=EPODOC&CC=GB&NR=1243160A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEOPOLD REICHL</creatorcontrib><creatorcontrib>HERMANN WEBER</creatorcontrib><creatorcontrib>ROBERT VACHENAUER</creatorcontrib><creatorcontrib>FRITZ KOEDERITZ</creatorcontrib><creatorcontrib>HELMUT PAINKE</creatorcontrib><creatorcontrib>HANS HERMANN LAMPE</creatorcontrib><creatorcontrib>EDWIN VOGT</creatorcontrib><creatorcontrib>GUNTER KNAUFT</creatorcontrib><title>IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS</title><description>1,243,160. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 8 May, 1970 [30 May, 1969], No. 22256/70. Heading G4A. A data processing system includes a CPU, ancillary (e.g. I/O) units connected thereto by a ring bus system comprising an address bus and a data bus, and switching means selectively operable in response to a signal indicative of the absence of execution of a programme instruction involving communication between the CPU and the ancillary units, to apply an address of an ancillary unit defined by manually settable test means to the address bus, the addressed unit supplying data via the data bus to the CPU. The switching means only operates in response to the signal in this way if a manual mode switch is set to "I/O display", the data sent to the CPU being sense data which is displayed on lamps on the CPU control panel. If the mode switch is set to "I/O status stop", then in the presence of the "signal" mentioned above, the machine stops (i.e. at the address defined by the manually settable test means) when the contents of the data bus equal the setting of further manual switches. When test and maintenance work as above is not being performed, the manually settable test means and the further manual switches are used as conventional address and data configuration switches, and the lamps are used for displaying register and storage contents.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1971</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD39A0I8g9z9XX1CwlW8PRTcPRzUQhy9XEM8fRzVwjxV3BxDHFUACpxdg0OBgkFRwaHuPoG8zCwpiXmFKfyQmluBnk31xBnD93Ugvz41OKCxOTUvNSSeHcnQyMTY0MzA0djwioAr0QnZw</recordid><startdate>19710818</startdate><enddate>19710818</enddate><creator>LEOPOLD REICHL</creator><creator>HERMANN WEBER</creator><creator>ROBERT VACHENAUER</creator><creator>FRITZ KOEDERITZ</creator><creator>HELMUT PAINKE</creator><creator>HANS HERMANN LAMPE</creator><creator>EDWIN VOGT</creator><creator>GUNTER KNAUFT</creator><scope>EVB</scope></search><sort><creationdate>19710818</creationdate><title>IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS</title><author>LEOPOLD REICHL ; HERMANN WEBER ; ROBERT VACHENAUER ; FRITZ KOEDERITZ ; HELMUT PAINKE ; HANS HERMANN LAMPE ; EDWIN VOGT ; GUNTER KNAUFT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_GB1243160A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1971</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>LEOPOLD REICHL</creatorcontrib><creatorcontrib>HERMANN WEBER</creatorcontrib><creatorcontrib>ROBERT VACHENAUER</creatorcontrib><creatorcontrib>FRITZ KOEDERITZ</creatorcontrib><creatorcontrib>HELMUT PAINKE</creatorcontrib><creatorcontrib>HANS HERMANN LAMPE</creatorcontrib><creatorcontrib>EDWIN VOGT</creatorcontrib><creatorcontrib>GUNTER KNAUFT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEOPOLD REICHL</au><au>HERMANN WEBER</au><au>ROBERT VACHENAUER</au><au>FRITZ KOEDERITZ</au><au>HELMUT PAINKE</au><au>HANS HERMANN LAMPE</au><au>EDWIN VOGT</au><au>GUNTER KNAUFT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS</title><date>1971-08-18</date><risdate>1971</risdate><abstract>1,243,160. Data processing. INTERNATIONAL BUSINESS MACHINES CORP. 8 May, 1970 [30 May, 1969], No. 22256/70. Heading G4A. A data processing system includes a CPU, ancillary (e.g. I/O) units connected thereto by a ring bus system comprising an address bus and a data bus, and switching means selectively operable in response to a signal indicative of the absence of execution of a programme instruction involving communication between the CPU and the ancillary units, to apply an address of an ancillary unit defined by manually settable test means to the address bus, the addressed unit supplying data via the data bus to the CPU. The switching means only operates in response to the signal in this way if a manual mode switch is set to "I/O display", the data sent to the CPU being sense data which is displayed on lamps on the CPU control panel. If the mode switch is set to "I/O status stop", then in the presence of the "signal" mentioned above, the machine stops (i.e. at the address defined by the manually settable test means) when the contents of the data bus equal the setting of further manual switches. When test and maintenance work as above is not being performed, the manually settable test means and the further manual switches are used as conventional address and data configuration switches, and the lamps are used for displaying register and storage contents.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | IMPROVEMENTS IN AND RELATING TO DATA PROCESSING SYSTEMS |
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