PROCEDE DE FABRICATION D'UN CIRCUIT INTEGRE ET NOTAMMENT D'UNE MEMOIRE EPROM COMPORTANT DEUX COMPOSANTS DISTINCTS ISOLES ELECTRIQUEMENT

PROCEDE DE FABRICATION D'UN CIRCUIT INTEGRE ET NOTAMMENT D'UNE MEMOIRE EPROM COMPORTANT DEUX COMPOSANTS DISTINCTS ISOLES ELECTRIQUEMENT.CE PROCEDE CONSISTE A REALISER UN POINT MEMOIRE COMPORTANT UN PREMIER ISOLANT, UNE PREMIERE GRILLE, UN SECOND ISOLANT ET UNE SECONDE GRILLE EMPILES, ET UN CIRCUIT PERIPHERIQUE COMPORTANT UN TROISIEME ISOLANT ET UNE TROISIEME GRILLE EN DEPOSANT SUR LE SUBSTRAT 8 UNE COUCHE 110 DE PREMIER ISOLANT, UNE PREMIERE COUCHE CONDUCTRICE 112, UNE COUCHE DE SECOND ISOLANT 116, GRAVANT LA COUCHE DE SECOND ISOLANT ET DE LA PREMIERE COUCHE CONDUCTRICE POUR NE GARDER DU SECOND ISOLANT ET DU MATERIAU CONDUCTEUR QU'A L'ENDROIT OU SERA REALISE LE PREMIER COMPOSANT, ELIMINANT LES REGIONS DE LA COUCHE DE PREMIER ISOLANT MISES A NU, DEPOSANT LE TROISIEME ISOLANT 130 A L'ENDROIT OU SERA REALISE LE SECOND COMPOSANT, DEPOSANT UNE SECONDE COUCHE CONDUCTRICE 114, REALISANT LA SECONDE ET LA TROISIEME GRILLE, PAR GRAVURE DE LA SECONDE COUCHE CONDUCTRICE, ET LA PREMIERE GRILLE PAR UNE SECONDE GRAVURE DE LA COUCHE DE SECOND ISOLANT ET DE LA PREMIERE COUCHE CONDUCTRICE. 1. Process for the production, on a semiconductor substrate (8), of an integrated circuit having at least two separate electrically insulated components, a first component (2) having a first insulant (10) surmounted by first (12) and second (14) stacked gates, which are separated by a second insulant (16), and a second component (22) having a third insulant (30) surmounted by a third gate (28), the first (10), second (16) and third (30) insulants having different, clearly defined thicknesses, characterized in that it comprises the following stages : a) producing a first insulant layer (110) on the substrate (8), b) covering the first insulant layer (110) with a first conductive layer (112), in which the first gate (12) will be formed, c) formation of a second insulant layer (112) on the first conductive layer (116), d) carrying out a first etching of the second insulant layer (116) and the first conductive layer (112) so as to only retain said second insulant and said conductive material in the region in which the first component will be produced, e) elimination of the first insulant layer (110) region located at the point where the second component will be produced, f) producing a third insulant layer (130) in said location, g) covering the structure obtained with a second conductive layer (114), h) producing the second (14) and third (28) gates by etching the second conductive layer (11