SYSTEME DE TRAITEMENT MODULAIRE, SE PRETANT A DE MULTIPLES CONFIGURATIONS INTEGRE AVEC UN SYSTEME DE PRE-TRAITEMENT

Un système de traitement modulaire, se prêtant à de multiples configurations et intégré avec un système de pré-traitement téléphonique. Il se compose de types de modules élémentaires I, M, CPU, MEI, MAC, dont chacun est interconnecté dans des structures de traitement, le module qui remplit la foncti...

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1. Verfasser: RICCARDO CEDOLIN, WOLMET CHIAROTTINO, GIUSEPPE GIANDONATO, SILVANO GIORCELLI, GIORGIO MARTINENGO, GIORGIO SOFI, SERGIO VILLONE
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creator RICCARDO CEDOLIN, WOLMET CHIAROTTINO, GIUSEPPE GIANDONATO, SILVANO GIORCELLI, GIORGIO MARTINENGO, GIORGIO SOFI, SERGIO VILLONE
description Un système de traitement modulaire, se prêtant à de multiples configurations et intégré avec un système de pré-traitement téléphonique. Il se compose de types de modules élémentaires I, M, CPU, MEI, MAC, dont chacun est interconnecté dans des structures de traitement, le module qui remplit la fonction d'unité centrale CPU est conçu pour être > par une seule unité de traitement et dans chacune des unités de traitement, il est prévu des moyens propres à effectuer le pré-traitement en temps réel de signaux téléphoniques. A signal-processing system, e.g. for a telephone exchange, comprises n modular processing units each including a pair of identical microprocessors operating in parallel on binary signals arriving over an internal bus, only one microprocessor of each pair being enabled to transmit outgoing messages to that bus while the other operates as a dummy. The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. The processing units may be hierarchically organized in several tiers of different ranks.
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The two microprocessors are interlinked by a correlating connection enabling verification of their correct operation in response to microinstructions read out from respective microprogram memories thereof under the control of a common clock. A momentary divergence, resulting from a relative lag in the response of one microprocessor to an asynchronously arriving signal bit, results in a delay of the microprogram by one clock cycle to permit resynchronization; longer-lasting disparities lead to a deactivation of the microprocessor pair and to the emission of an alarm signal. Processing information individual to the associated peripheral unit is stored in an internal memory connected to the bus; general information utilizable by any processing unit is stored in several outside memory banks accessible through external extensions of the internal bus of any such unit. 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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
SELECTING
title SYSTEME DE TRAITEMENT MODULAIRE, SE PRETANT A DE MULTIPLES CONFIGURATIONS INTEGRE AVEC UN SYSTEME DE PRE-TRAITEMENT
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