Input and output interface logic for concurrent operations - permits simultaneous transfer of command, peripheral address and data
The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data. It includes logic in a peripheral device control unit, for dynamic change of the attached peripheral device interrupt priority level while the device may be...
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creator | DONALL G. BOURKE, LOUIS P. VERGARI ET MICHAEL I. DAVIS |
description | The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data. It includes logic in a peripheral device control unit, for dynamic change of the attached peripheral device interrupt priority level while the device may be executing a prior command. The I/O control logic includes means for initiating serial poll signalling while other transfers are taking place on the interface. Pref. this is achieved by utilizing the data transfer lines of the interface for data involved in the transfer, while utilizing a separate address bus for simultaneous transfer to a peripheral device control unit of a device address to be used for selection, and command information involved in the transfer. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_FR2349883A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>FR2349883A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_FR2349883A13</originalsourceid><addsrcrecordid>eNqNjrEOwjAMRLswIOAf_AF0gDKUESEqWBF7ZbUORErtKHZ-gC8nRXwA091w7-6W1fvGMRsgjyDZZuvZKDkcCII8_QBOEgzCQ06J2EAiJTQvrFBD8ZM3BfVTDoZMkhUsIaujBOIKOE2lezsnfXwVNACOYyLV7-aIhutq4TAobX66qqC7PM7XmqL0pLFcYbK-u--bw7Ftm9Ou-SPyAbHUSkA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Input and output interface logic for concurrent operations - permits simultaneous transfer of command, peripheral address and data</title><source>esp@cenet</source><creator>DONALL G. BOURKE, LOUIS P. VERGARI ET MICHAEL I. DAVIS</creator><creatorcontrib>DONALL G. BOURKE, LOUIS P. VERGARI ET MICHAEL I. DAVIS</creatorcontrib><description>The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data. It includes logic in a peripheral device control unit, for dynamic change of the attached peripheral device interrupt priority level while the device may be executing a prior command. The I/O control logic includes means for initiating serial poll signalling while other transfers are taking place on the interface. Pref. this is achieved by utilizing the data transfer lines of the interface for data involved in the transfer, while utilizing a separate address bus for simultaneous transfer to a peripheral device control unit of a device address to be used for selection, and command information involved in the transfer.</description><language>eng ; fre</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>1977</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19771125&DB=EPODOC&CC=FR&NR=2349883A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19771125&DB=EPODOC&CC=FR&NR=2349883A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DONALL G. BOURKE, LOUIS P. VERGARI ET MICHAEL I. DAVIS</creatorcontrib><title>Input and output interface logic for concurrent operations - permits simultaneous transfer of command, peripheral address and data</title><description>The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data. It includes logic in a peripheral device control unit, for dynamic change of the attached peripheral device interrupt priority level while the device may be executing a prior command. The I/O control logic includes means for initiating serial poll signalling while other transfers are taking place on the interface. Pref. this is achieved by utilizing the data transfer lines of the interface for data involved in the transfer, while utilizing a separate address bus for simultaneous transfer to a peripheral device control unit of a device address to be used for selection, and command information involved in the transfer.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1977</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjrEOwjAMRLswIOAf_AF0gDKUESEqWBF7ZbUORErtKHZ-gC8nRXwA091w7-6W1fvGMRsgjyDZZuvZKDkcCII8_QBOEgzCQ06J2EAiJTQvrFBD8ZM3BfVTDoZMkhUsIaujBOIKOE2lezsnfXwVNACOYyLV7-aIhutq4TAobX66qqC7PM7XmqL0pLFcYbK-u--bw7Ftm9Ou-SPyAbHUSkA</recordid><startdate>19771125</startdate><enddate>19771125</enddate><creator>DONALL G. BOURKE, LOUIS P. VERGARI ET MICHAEL I. DAVIS</creator><scope>EVB</scope></search><sort><creationdate>19771125</creationdate><title>Input and output interface logic for concurrent operations - permits simultaneous transfer of command, peripheral address and data</title><author>DONALL G. BOURKE, LOUIS P. VERGARI ET MICHAEL I. DAVIS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_FR2349883A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>1977</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>DONALL G. BOURKE, LOUIS P. VERGARI ET MICHAEL I. DAVIS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DONALL G. BOURKE, LOUIS P. VERGARI ET MICHAEL I. DAVIS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Input and output interface logic for concurrent operations - permits simultaneous transfer of command, peripheral address and data</title><date>1977-11-25</date><risdate>1977</risdate><abstract>The interface between I/O control logic, or channel, and peripheral devices permits simultaneous transfer of command, device address, and data. It includes logic in a peripheral device control unit, for dynamic change of the attached peripheral device interrupt priority level while the device may be executing a prior command. The I/O control logic includes means for initiating serial poll signalling while other transfers are taking place on the interface. Pref. this is achieved by utilizing the data transfer lines of the interface for data involved in the transfer, while utilizing a separate address bus for simultaneous transfer to a peripheral device control unit of a device address to be used for selection, and command information involved in the transfer.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Input and output interface logic for concurrent operations - permits simultaneous transfer of command, peripheral address and data |
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