PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD
A printed wiring board includes: a dielectric layer having a main surface; and a conductive pattern. The conductive pattern includes a metal layer that is disposed on the main surface, an electroless plating layer that is disposed on the metal layer, and an electrolytic plating layer that is dispose...
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creator | MIYATA, Kazuhiro KIYA, Satoshi NITTA, Koji SAKAI, Shoichiro |
description | A printed wiring board includes: a dielectric layer having a main surface; and a conductive pattern. The conductive pattern includes a metal layer that is disposed on the main surface, an electroless plating layer that is disposed on the metal layer, and an electrolytic plating layer that is disposed on the electroless plating layer. An average thickness of the metal layer is 2.1 µm or more and 9.0 µm or less. Maximum height roughness of a surface of the metal layer opposed to the main surface is 5.0 µm or less. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP4462964A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP4462964A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP4462964A13</originalsourceid><addsrcrecordid>eNrjZHALCPL0C3F1UQj3BDLcFZz8HYNcFBz9XBR8XUM8_F0U3PyDFHwd_ULdHJ1DQsFKsOngYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgEmJmZGlmYmjobGRCgBAFGVK-Y</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD</title><source>esp@cenet</source><creator>MIYATA, Kazuhiro ; KIYA, Satoshi ; NITTA, Koji ; SAKAI, Shoichiro</creator><creatorcontrib>MIYATA, Kazuhiro ; KIYA, Satoshi ; NITTA, Koji ; SAKAI, Shoichiro</creatorcontrib><description>A printed wiring board includes: a dielectric layer having a main surface; and a conductive pattern. The conductive pattern includes a metal layer that is disposed on the main surface, an electroless plating layer that is disposed on the metal layer, and an electrolytic plating layer that is disposed on the electroless plating layer. An average thickness of the metal layer is 2.1 µm or more and 9.0 µm or less. Maximum height roughness of a surface of the metal layer opposed to the main surface is 5.0 µm or less.</description><language>eng ; fre ; ger</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241113&DB=EPODOC&CC=EP&NR=4462964A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20241113&DB=EPODOC&CC=EP&NR=4462964A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MIYATA, Kazuhiro</creatorcontrib><creatorcontrib>KIYA, Satoshi</creatorcontrib><creatorcontrib>NITTA, Koji</creatorcontrib><creatorcontrib>SAKAI, Shoichiro</creatorcontrib><title>PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD</title><description>A printed wiring board includes: a dielectric layer having a main surface; and a conductive pattern. The conductive pattern includes a metal layer that is disposed on the main surface, an electroless plating layer that is disposed on the metal layer, and an electrolytic plating layer that is disposed on the electroless plating layer. An average thickness of the metal layer is 2.1 µm or more and 9.0 µm or less. Maximum height roughness of a surface of the metal layer opposed to the main surface is 5.0 µm or less.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHALCPL0C3F1UQj3BDLcFZz8HYNcFBz9XBR8XUM8_F0U3PyDFHwd_ULdHJ1DQsFKsOngYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgEmJmZGlmYmjobGRCgBAFGVK-Y</recordid><startdate>20241113</startdate><enddate>20241113</enddate><creator>MIYATA, Kazuhiro</creator><creator>KIYA, Satoshi</creator><creator>NITTA, Koji</creator><creator>SAKAI, Shoichiro</creator><scope>EVB</scope></search><sort><creationdate>20241113</creationdate><title>PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD</title><author>MIYATA, Kazuhiro ; KIYA, Satoshi ; NITTA, Koji ; SAKAI, Shoichiro</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4462964A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2024</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>MIYATA, Kazuhiro</creatorcontrib><creatorcontrib>KIYA, Satoshi</creatorcontrib><creatorcontrib>NITTA, Koji</creatorcontrib><creatorcontrib>SAKAI, Shoichiro</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MIYATA, Kazuhiro</au><au>KIYA, Satoshi</au><au>NITTA, Koji</au><au>SAKAI, Shoichiro</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD</title><date>2024-11-13</date><risdate>2024</risdate><abstract>A printed wiring board includes: a dielectric layer having a main surface; and a conductive pattern. The conductive pattern includes a metal layer that is disposed on the main surface, an electroless plating layer that is disposed on the metal layer, and an electrolytic plating layer that is disposed on the electroless plating layer. An average thickness of the metal layer is 2.1 µm or more and 9.0 µm or less. Maximum height roughness of a surface of the metal layer opposed to the main surface is 5.0 µm or less.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS |
title | PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD |
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