INTEGRATED CIRCUIT DEVICES INCLUDING INTERGATE SPACER AND METHODS OF FABRICATION THE SAME

An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower cha...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SEO, Kang-Ill, YUN, Seungchan, BAEK, Jaejik
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SEO, Kang-Ill
YUN, Seungchan
BAEK, Jaejik
description An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower channel region, an intergate spacer comprising an insulating material and adjacent to a side surface of the lower channel region, and a gate layer. The intergate spacer may be between the side surface of the lower channel region and the gate layer.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP4459672A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP4459672A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP4459672A13</originalsourceid><addsrcrecordid>eNqNyrEKwjAQANAuDqL-w_2Ag1qVjuflkh7YtCRXwakUiZNoof4_VvADnN7y5tlVvLILqGyAJFArCoYvQhxBPJ1bI97BNwU3JYgNEgdAb6BiLWsTobZg8RSEUKX2oOW0sOJlNrv3jzGtfi4ysKxUrtPw6tI49Lf0TO-OmzzfF4fjFje7P8oHsFow8g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INTEGRATED CIRCUIT DEVICES INCLUDING INTERGATE SPACER AND METHODS OF FABRICATION THE SAME</title><source>esp@cenet</source><creator>SEO, Kang-Ill ; YUN, Seungchan ; BAEK, Jaejik</creator><creatorcontrib>SEO, Kang-Ill ; YUN, Seungchan ; BAEK, Jaejik</creatorcontrib><description>An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower channel region, an intergate spacer comprising an insulating material and adjacent to a side surface of the lower channel region, and a gate layer. The intergate spacer may be between the side surface of the lower channel region and the gate layer.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES ; NANOTECHNOLOGY ; PERFORMING OPERATIONS ; SEMICONDUCTOR DEVICES ; SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES ; TRANSPORTING</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241106&amp;DB=EPODOC&amp;CC=EP&amp;NR=4459672A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20241106&amp;DB=EPODOC&amp;CC=EP&amp;NR=4459672A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SEO, Kang-Ill</creatorcontrib><creatorcontrib>YUN, Seungchan</creatorcontrib><creatorcontrib>BAEK, Jaejik</creatorcontrib><title>INTEGRATED CIRCUIT DEVICES INCLUDING INTERGATE SPACER AND METHODS OF FABRICATION THE SAME</title><description>An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower channel region, an intergate spacer comprising an insulating material and adjacent to a side surface of the lower channel region, and a gate layer. The intergate spacer may be between the side surface of the lower channel region and the gate layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OR TREATMENT OF NANOSTRUCTURES</subject><subject>MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES</subject><subject>NANOTECHNOLOGY</subject><subject>PERFORMING OPERATIONS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQANAuDqL-w_2Ag1qVjuflkh7YtCRXwakUiZNoof4_VvADnN7y5tlVvLILqGyAJFArCoYvQhxBPJ1bI97BNwU3JYgNEgdAb6BiLWsTobZg8RSEUKX2oOW0sOJlNrv3jzGtfi4ysKxUrtPw6tI49Lf0TO-OmzzfF4fjFje7P8oHsFow8g</recordid><startdate>20241106</startdate><enddate>20241106</enddate><creator>SEO, Kang-Ill</creator><creator>YUN, Seungchan</creator><creator>BAEK, Jaejik</creator><scope>EVB</scope></search><sort><creationdate>20241106</creationdate><title>INTEGRATED CIRCUIT DEVICES INCLUDING INTERGATE SPACER AND METHODS OF FABRICATION THE SAME</title><author>SEO, Kang-Ill ; YUN, Seungchan ; BAEK, Jaejik</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4459672A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OR TREATMENT OF NANOSTRUCTURES</topic><topic>MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES</topic><topic>NANOTECHNOLOGY</topic><topic>PERFORMING OPERATIONS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>SEO, Kang-Ill</creatorcontrib><creatorcontrib>YUN, Seungchan</creatorcontrib><creatorcontrib>BAEK, Jaejik</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SEO, Kang-Ill</au><au>YUN, Seungchan</au><au>BAEK, Jaejik</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INTEGRATED CIRCUIT DEVICES INCLUDING INTERGATE SPACER AND METHODS OF FABRICATION THE SAME</title><date>2024-11-06</date><risdate>2024</risdate><abstract>An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower channel region, an intergate spacer comprising an insulating material and adjacent to a side surface of the lower channel region, and a gate layer. The intergate spacer may be between the side surface of the lower channel region and the gate layer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP4459672A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES
NANOTECHNOLOGY
PERFORMING OPERATIONS
SEMICONDUCTOR DEVICES
SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES
TRANSPORTING
title INTEGRATED CIRCUIT DEVICES INCLUDING INTERGATE SPACER AND METHODS OF FABRICATION THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T06%3A25%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SEO,%20Kang-Ill&rft.date=2024-11-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP4459672A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true