HARDWARE FOR END-TO-END COMMUNICATION PROTECTION IN ASIC
An apparatus comprising communication logic and a memory. The communication logic may be configured to receive a data payload, validate the data payload, decode an instruction from the data payload, generate a bypass signal in response to the instruction and generate a remote signal in response to a...
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| creator | GRAMENOS, James ISLIM, Haitham FITZPATRICK, John WANTUCK, Ron |
| description | An apparatus comprising communication logic and a memory. The communication logic may be configured to receive a data payload, validate the data payload, decode an instruction from the data payload, generate a bypass signal in response to the instruction and generate a remote signal in response to an arm signal. The memory may be configured to store configuration data and store status information. The bypass signal may be compatible with a safing block configured to provide one independent signal for an actuator. The communication logic may operate according to a pre-defined end-to-end communication standard. The configuration data may be configured to enable a selected profile for the pre-defined end-to-end communication standard. The safing block may be configured to pass through the bypass signal generated by the communication logic as the arm signal. The communication logic may receive the arm signal from the safing block. |
| format | Patent |
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| language | eng ; fre ; ger |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | HARDWARE FOR END-TO-END COMMUNICATION PROTECTION IN ASIC |
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