INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A PACKAGE SUBSTRATE WITH A DOUBLE SIDE EMBEDDED TRACE SUBSTRATE (ETS), AND RELATED FABRICATION METHODS

INTEGRATED CIRCUIT (IC) PACKAGES EMPLOYING A PACKAGE SUBSTRATE WITH A DOUBLE SIDE EMBEDDED TRACE SUBSTRATE (ETS), AND RELATED FABRICATION METHODS

Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods. To facilitate providing a reduced thickness substrate in the IC package to reduce overall height of the IC package while supporting higher density input/...

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Bibliographische Detailangaben
Hauptverfasser: PATIL, Aniket, KANG, Kuiwon, KIM, Michelle Yejin, BUOT, Joan Rey Villarba, WE, Hong Bok
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods. To facilitate providing a reduced thickness substrate in the IC package to reduce overall height of the IC package while supporting higher density input/output (I/O) connections, a package substrate in the IC package includes a double side ETS. A double side ETS includes two (2) adjacent ETS metallization layers that both include metal traces embedded in an insulating layer. The embedded metal traces in the ETS metallization layers of the double side ETS can be electrically coupled to each other through vertical interconnect accesses (vias) (e.g., metal pillars, metal posts) to provide signal routing paths between embedded metal traces in the ETS metallization layers.