A SIGE HBT AND METHODS OF MANUFACTURING THE SAME
Disclosed is a SiGe heterojunction bipolar transistor, HBT, and method of manufacturing the same, comprising: an n-doped buried collector (HV); a p-doped epitaxial monocrystalline SiGe base layer, within a layer stack, the layer stack (110) being over and in direct contact with the collector (HV); a...
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creator | Donkers, Johannes Josephus Theodorus Marinus John, Jay Paul Kirchgessner, James Albert Sebel, Patrick |
description | Disclosed is a SiGe heterojunction bipolar transistor, HBT, and method of manufacturing the same, comprising: an n-doped buried collector (HV); a p-doped epitaxial monocrystalline SiGe base layer, within a layer stack, the layer stack (110) being over and in direct contact with the collector (HV); an n-doped monocrystalline silicon emitter (142) over a first area of the layer stack (110), the emitter provided with a polycrystalline silicon emitter contact layer (144) thereon; an epitaxial silicon base contact layer (218) over a second area of the layer stack (110); an oxide layer (216) over a third area of the layer stack between the first and second areas, wherein the oxide layer (216) and the n-doped monocrystalline silicon emitter (142) are within a window in the epitaxial silicon base contact layer (218), the window having sidewalls; dielectric spacers (132) on the sidewalls of the window and over the oxide layer (216), and providing electrical isolation between the epitaxial silicon layer (218) and the polycrystalline silicon layer (144); the epitaxial silicon layer (218) extending beneath the dielectric spacers (132) on the sidewalls of the window and extending upward (218d) between the dielectric spacers (132) and a further dielectric layer (120). |
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a p-doped epitaxial monocrystalline SiGe base layer, within a layer stack, the layer stack (110) being over and in direct contact with the collector (HV); an n-doped monocrystalline silicon emitter (142) over a first area of the layer stack (110), the emitter provided with a polycrystalline silicon emitter contact layer (144) thereon; an epitaxial silicon base contact layer (218) over a second area of the layer stack (110); an oxide layer (216) over a third area of the layer stack between the first and second areas, wherein the oxide layer (216) and the n-doped monocrystalline silicon emitter (142) are within a window in the epitaxial silicon base contact layer (218), the window having sidewalls; dielectric spacers (132) on the sidewalls of the window and over the oxide layer (216), and providing electrical isolation between the epitaxial silicon layer (218) and the polycrystalline silicon layer (144); the epitaxial silicon layer (218) extending beneath the dielectric spacers (132) on the sidewalls of the window and extending upward (218d) between the dielectric spacers (132) and a further dielectric layer (120).</description><language>eng ; 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John, Jay Paul ; Kirchgessner, James Albert ; Sebel, Patrick</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4428923A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Donkers, Johannes Josephus Theodorus Marinus</creatorcontrib><creatorcontrib>John, Jay Paul</creatorcontrib><creatorcontrib>Kirchgessner, James Albert</creatorcontrib><creatorcontrib>Sebel, Patrick</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Donkers, Johannes Josephus Theodorus Marinus</au><au>John, Jay Paul</au><au>Kirchgessner, James Albert</au><au>Sebel, Patrick</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>A SIGE HBT AND METHODS OF MANUFACTURING THE SAME</title><date>2024-09-11</date><risdate>2024</risdate><abstract>Disclosed is a SiGe heterojunction bipolar transistor, HBT, and method of manufacturing the same, comprising: an n-doped buried collector (HV); a p-doped epitaxial monocrystalline SiGe base layer, within a layer stack, the layer stack (110) being over and in direct contact with the collector (HV); an n-doped monocrystalline silicon emitter (142) over a first area of the layer stack (110), the emitter provided with a polycrystalline silicon emitter contact layer (144) thereon; an epitaxial silicon base contact layer (218) over a second area of the layer stack (110); an oxide layer (216) over a third area of the layer stack between the first and second areas, wherein the oxide layer (216) and the n-doped monocrystalline silicon emitter (142) are within a window in the epitaxial silicon base contact layer (218), the window having sidewalls; dielectric spacers (132) on the sidewalls of the window and over the oxide layer (216), and providing electrical isolation between the epitaxial silicon layer (218) and the polycrystalline silicon layer (144); the epitaxial silicon layer (218) extending beneath the dielectric spacers (132) on the sidewalls of the window and extending upward (218d) between the dielectric spacers (132) and a further dielectric layer (120).</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | A SIGE HBT AND METHODS OF MANUFACTURING THE SAME |
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