MEMORY TRANSACTION MANAGEMENT

MEMORY TRANSACTION MANAGEMENT

A device includes a processor coupled to a memory. The processor is configured to assign distinct domain identifiers to each of multiple software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associa...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KOOB, Christopher, MORA, Venkatarami
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A device includes a processor coupled to a memory. The processor is configured to assign distinct domain identifiers to each of multiple software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associated with a domain identifier.