PROCESSOR AND OPERATING METHOD THEREOF

PROCESSOR AND OPERATING METHOD THEREOF

A processor includes a register file, a context controller that, in response to a target interrupt occurring, is configured to determine, a target register that stores new data acquired through each of commands for executing an interrupt service routine (ISR) among the plurality of registers, a writ...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: KIM, Hyunpil, SIM, Hyunwoo, AHN, Seongwoo
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator KIM, Hyunpil
SIM, Hyunwoo
AHN, Seongwoo
description A processor includes a register file, a context controller that, in response to a target interrupt occurring, is configured to determine, a target register that stores new data acquired through each of commands for executing an interrupt service routine (ISR) among the plurality of registers, a write buffer configured to transmit pre-data stored in the target register to a memory, and a flag register configured to store set data including set values indicating whether the new data is stored in each of the registers. The context controller is configured to determine whether to transfer the pre-data to the memory through the write buffer based on the set data.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP4411537A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP4411537A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP4411537A13</originalsourceid><addsrcrecordid>eNrjZFALCPJ3dg0O9g9ScPRzUfAPcA1yDPH0c1fwdQ3x8HdRCPFwDXL1d-NhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGuASYmhoamxuaOhsZEKAEAhj0jMQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PROCESSOR AND OPERATING METHOD THEREOF</title><source>esp@cenet</source><creator>KIM, Hyunpil ; SIM, Hyunwoo ; AHN, Seongwoo</creator><creatorcontrib>KIM, Hyunpil ; SIM, Hyunwoo ; AHN, Seongwoo</creatorcontrib><description>A processor includes a register file, a context controller that, in response to a target interrupt occurring, is configured to determine, a target register that stores new data acquired through each of commands for executing an interrupt service routine (ISR) among the plurality of registers, a write buffer configured to transmit pre-data stored in the target register to a memory, and a flag register configured to store set data including set values indicating whether the new data is stored in each of the registers. The context controller is configured to determine whether to transfer the pre-data to the memory through the write buffer based on the set data.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240807&amp;DB=EPODOC&amp;CC=EP&amp;NR=4411537A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240807&amp;DB=EPODOC&amp;CC=EP&amp;NR=4411537A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KIM, Hyunpil</creatorcontrib><creatorcontrib>SIM, Hyunwoo</creatorcontrib><creatorcontrib>AHN, Seongwoo</creatorcontrib><title>PROCESSOR AND OPERATING METHOD THEREOF</title><description>A processor includes a register file, a context controller that, in response to a target interrupt occurring, is configured to determine, a target register that stores new data acquired through each of commands for executing an interrupt service routine (ISR) among the plurality of registers, a write buffer configured to transmit pre-data stored in the target register to a memory, and a flag register configured to store set data including set values indicating whether the new data is stored in each of the registers. The context controller is configured to determine whether to transfer the pre-data to the memory through the write buffer based on the set data.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFALCPJ3dg0O9g9ScPRzUfAPcA1yDPH0c1fwdQ3x8HdRCPFwDXL1d-NhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGuASYmhoamxuaOhsZEKAEAhj0jMQ</recordid><startdate>20240807</startdate><enddate>20240807</enddate><creator>KIM, Hyunpil</creator><creator>SIM, Hyunwoo</creator><creator>AHN, Seongwoo</creator><scope>EVB</scope></search><sort><creationdate>20240807</creationdate><title>PROCESSOR AND OPERATING METHOD THEREOF</title><author>KIM, Hyunpil ; SIM, Hyunwoo ; AHN, Seongwoo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4411537A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>KIM, Hyunpil</creatorcontrib><creatorcontrib>SIM, Hyunwoo</creatorcontrib><creatorcontrib>AHN, Seongwoo</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KIM, Hyunpil</au><au>SIM, Hyunwoo</au><au>AHN, Seongwoo</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PROCESSOR AND OPERATING METHOD THEREOF</title><date>2024-08-07</date><risdate>2024</risdate><abstract>A processor includes a register file, a context controller that, in response to a target interrupt occurring, is configured to determine, a target register that stores new data acquired through each of commands for executing an interrupt service routine (ISR) among the plurality of registers, a write buffer configured to transmit pre-data stored in the target register to a memory, and a flag register configured to store set data including set values indicating whether the new data is stored in each of the registers. The context controller is configured to determine whether to transfer the pre-data to the memory through the write buffer based on the set data.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP4411537A1
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title PROCESSOR AND OPERATING METHOD THEREOF
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T01%3A37%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KIM,%20Hyunpil&rft.date=2024-08-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP4411537A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true