COMMUNICATION LATENCY MITIGATION FOR ON-CHIP NETWORKS

This application relates to systems and methods for reduced latency in arrays of computing nodes. In some embodiments, a method of routing data can include outputting a first bypass signal and a second bypass signal from a first computing node of an array of computing nodes, wherein the first bypass...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	WILLIAMS, Douglas R
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
Online-Zugang:	Volltext bestellen
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