DIGITAL PHASE-LOCKED LOOP AND RELATED MERGED DUTY CYCLE CALIBRATION SCHEME FOR FREQUENCY SYNTHESIZERS

The techniques described herein relate to duty cycle error calibration. An example apparatus includes a multi-modulus divider (MMD) circuit configured to receive a first digital code corresponding to a first time delay and included in a first plurality of digital codes associated with a first range...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	ELMALLAH, Ahmed Safwat Mohamed Aboelenein, ABDULLATIF, Mohammed Mohsen Abdulsalam, ALI, Tamer Mohammed
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!