DUAL READ PORT LATCH ARRAY BIT CELL

An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charg...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WUU, John J, BANERJEE, Arijit, SCHREIBER, Russell
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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