STATIC RANDOM-ACCESS MEMORY (SRAM) ARRAY CIRCUITS INCLUDING BILATERAL WELL TAP CELLS WITH REDUCED WIDTH FOLDED FINGER STRUCTURE
An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between...
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creator | KODLIPET, Pradeep Jayadev DESAI, Channappa GAO, Yandong SHARMA, Sunil SRIKANTH, Anne |
description | An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP4315335A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP4315335A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP4315335A13</originalsourceid><addsrcrecordid>eNqNyzEKwkAQBdA0FqLeYUotLCTmAOPsRBd2kzA7S0gVRNZKNBB7r-4WHsDq_wf_L4tPUFRLINiY1u-RiEMAz76VAbZB0O8ARXAAskLRagDbkIvGNmc4WYfKgg56dg4UO6BcAvRWLyBsIrHJMFl160xGnX8sEFQiaRReF4v79TGnzS9XBdSsdNmn6TWmebre0jO9R-6O5aEqywoP5R-TL50zO1M</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>STATIC RANDOM-ACCESS MEMORY (SRAM) ARRAY CIRCUITS INCLUDING BILATERAL WELL TAP CELLS WITH REDUCED WIDTH FOLDED FINGER STRUCTURE</title><source>esp@cenet</source><creator>KODLIPET, Pradeep Jayadev ; DESAI, Channappa ; GAO, Yandong ; SHARMA, Sunil ; SRIKANTH, Anne</creator><creatorcontrib>KODLIPET, Pradeep Jayadev ; DESAI, Channappa ; GAO, Yandong ; SHARMA, Sunil ; SRIKANTH, Anne</creatorcontrib><description>An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate.</description><language>eng ; fre ; ger</language><subject>ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240207&DB=EPODOC&CC=EP&NR=4315335A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240207&DB=EPODOC&CC=EP&NR=4315335A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KODLIPET, Pradeep Jayadev</creatorcontrib><creatorcontrib>DESAI, Channappa</creatorcontrib><creatorcontrib>GAO, Yandong</creatorcontrib><creatorcontrib>SHARMA, Sunil</creatorcontrib><creatorcontrib>SRIKANTH, Anne</creatorcontrib><title>STATIC RANDOM-ACCESS MEMORY (SRAM) ARRAY CIRCUITS INCLUDING BILATERAL WELL TAP CELLS WITH REDUCED WIDTH FOLDED FINGER STRUCTURE</title><description>An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate.</description><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyzEKwkAQBdA0FqLeYUotLCTmAOPsRBd2kzA7S0gVRNZKNBB7r-4WHsDq_wf_L4tPUFRLINiY1u-RiEMAz76VAbZB0O8ARXAAskLRagDbkIvGNmc4WYfKgg56dg4UO6BcAvRWLyBsIrHJMFl160xGnX8sEFQiaRReF4v79TGnzS9XBdSsdNmn6TWmebre0jO9R-6O5aEqywoP5R-TL50zO1M</recordid><startdate>20240207</startdate><enddate>20240207</enddate><creator>KODLIPET, Pradeep Jayadev</creator><creator>DESAI, Channappa</creator><creator>GAO, Yandong</creator><creator>SHARMA, Sunil</creator><creator>SRIKANTH, Anne</creator><scope>EVB</scope></search><sort><creationdate>20240207</creationdate><title>STATIC RANDOM-ACCESS MEMORY (SRAM) ARRAY CIRCUITS INCLUDING BILATERAL WELL TAP CELLS WITH REDUCED WIDTH FOLDED FINGER STRUCTURE</title><author>KODLIPET, Pradeep Jayadev ; DESAI, Channappa ; GAO, Yandong ; SHARMA, Sunil ; SRIKANTH, Anne</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4315335A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2024</creationdate><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>KODLIPET, Pradeep Jayadev</creatorcontrib><creatorcontrib>DESAI, Channappa</creatorcontrib><creatorcontrib>GAO, Yandong</creatorcontrib><creatorcontrib>SHARMA, Sunil</creatorcontrib><creatorcontrib>SRIKANTH, Anne</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KODLIPET, Pradeep Jayadev</au><au>DESAI, Channappa</au><au>GAO, Yandong</au><au>SHARMA, Sunil</au><au>SRIKANTH, Anne</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>STATIC RANDOM-ACCESS MEMORY (SRAM) ARRAY CIRCUITS INCLUDING BILATERAL WELL TAP CELLS WITH REDUCED WIDTH FOLDED FINGER STRUCTURE</title><date>2024-02-07</date><risdate>2024</risdate><abstract>An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate.</abstract><oa>free_for_read</oa></addata></record> |
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language | eng ; fre ; ger |
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subjects | ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES |
title | STATIC RANDOM-ACCESS MEMORY (SRAM) ARRAY CIRCUITS INCLUDING BILATERAL WELL TAP CELLS WITH REDUCED WIDTH FOLDED FINGER STRUCTURE |
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