ADAPTIVE DYNAMIC CLOCK AND VOLTAGE SCALING

ADAPTIVE DYNAMIC CLOCK AND VOLTAGE SCALING

In each of two or more pipelined subsystems, the relative amount of time that the processing cores are idle may be determined. If the idle ratio is below a threshold, the clock frequency and voltage may be adjusted using dynamic clock and voltage scaling (DCVS) based on a power limit. However, if th...

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Hauptverfasser: SEVERSON, Matthew, VERRILLI, Colin Beaton
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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VERRILLI, Colin Beaton
description In each of two or more pipelined subsystems, the relative amount of time that the processing cores are idle may be determined. If the idle ratio is below a threshold, the clock frequency and voltage may be adjusted using dynamic clock and voltage scaling (DCVS) based on a power limit. However, if the idle ratio exceeds the threshold, the clock frequency and voltage may be decreased without regard to the power limit.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title ADAPTIVE DYNAMIC CLOCK AND VOLTAGE SCALING
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