COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches respo...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	SRIVASTAVA, Ankit, MIRHAJ, Seyed Arash, WADHWA, Sameer, MOHAN, Suren, LI, Ren
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	SRIVASTAVA, Ankit MIRHAJ, Seyed Arash WADHWA, Sameer MOHAN, Suren LI, Ren
description	A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP4309176A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP4309176A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP4309176A13</originalsourceid><addsrcrecordid>eNrjZNB09vcNCA1x1fX00_V19fUPilQI9wzxUAhxDfJzBHIcnUM8wxxDPP39eBhY0xJzilN5oTQ3g4Kba4izh25qQX58anFBYnJqXmpJvGuAibGBpaG5maOhMRFKAAhEJE4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION</title><source>esp@cenet</source><creator>SRIVASTAVA, Ankit ; MIRHAJ, Seyed Arash ; WADHWA, Sameer ; MOHAN, Suren ; LI, Ren</creator><creatorcontrib>SRIVASTAVA, Ankit ; MIRHAJ, Seyed Arash ; WADHWA, Sameer ; MOHAN, Suren ; LI, Ren</creatorcontrib><description>A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240124&DB=EPODOC&CC=EP&NR=4309176A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240124&DB=EPODOC&CC=EP&NR=4309176A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SRIVASTAVA, Ankit</creatorcontrib><creatorcontrib>MIRHAJ, Seyed Arash</creatorcontrib><creatorcontrib>WADHWA, Sameer</creatorcontrib><creatorcontrib>MOHAN, Suren</creatorcontrib><creatorcontrib>LI, Ren</creatorcontrib><title>COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION</title><description>A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.</description><subject>CALCULATING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB09vcNCA1x1fX00_V19fUPilQI9wzxUAhxDfJzBHIcnUM8wxxDPP39eBhY0xJzilN5oTQ3g4Kba4izh25qQX58anFBYnJqXmpJvGuAibGBpaG5maOhMRFKAAhEJE4</recordid><startdate>20240124</startdate><enddate>20240124</enddate><creator>SRIVASTAVA, Ankit</creator><creator>MIRHAJ, Seyed Arash</creator><creator>WADHWA, Sameer</creator><creator>MOHAN, Suren</creator><creator>LI, Ren</creator><scope>EVB</scope></search><sort><creationdate>20240124</creationdate><title>COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION</title><author>SRIVASTAVA, Ankit ; MIRHAJ, Seyed Arash ; WADHWA, Sameer ; MOHAN, Suren ; LI, Ren</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4309176A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2024</creationdate><topic>CALCULATING</topic><topic>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>SRIVASTAVA, Ankit</creatorcontrib><creatorcontrib>MIRHAJ, Seyed Arash</creatorcontrib><creatorcontrib>WADHWA, Sameer</creatorcontrib><creatorcontrib>MOHAN, Suren</creatorcontrib><creatorcontrib>LI, Ren</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SRIVASTAVA, Ankit</au><au>MIRHAJ, Seyed Arash</au><au>WADHWA, Sameer</au><au>MOHAN, Suren</au><au>LI, Ren</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION</title><date>2024-01-24</date><risdate>2024</risdate><abstract>A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng ; fre ; ger
recordid	cdi_epo_espacenet_EP4309176A1
source	esp@cenet
subjects	CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING INFORMATION STORAGE PHYSICS STATIC STORES
title	COMPUTE-IN-MEMORY WITH TERNARY ACTIVATION
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T18%3A04%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SRIVASTAVA,%20Ankit&rft.date=2024-01-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP4309176A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true