CHANNEL LESS FLOOR-PLANNING IN INTEGRATED CIRCUITS

Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include ove...

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Bibliographische Detailangaben
Hauptverfasser: KRISHNAPPA, Madan, SANAKA, Venugopal, LAKSHMIPATHI, Vinod Kumar, SURIAMOORTHY, Babu, PATIBANDA, Pavan Kumar
Format: Patent
Sprache:eng ; fre ; ger
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Zusammenfassung:Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.