MEMORY APPLIANCES FOR MEMORY INTENSIVE OPERATIONS
Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to...
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| creator | DAYAN, Gal MAYER-WOLF, Ilan BETITO, Shai ZEYDE, Roman SRETER, Hillel SPEKTOR, Evgeny KOREN, Shay HILLEL, Eliad SITY, Elad BRAUDO, Shany |
| description | Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors. The one or more processor subunits are configured to receive a sparse vector indicator from a host external to the at least one computational memory chip and, based on the received sparse vector indicator and the one or more portions of the embedding table, generate one or more vector sums. |
| format | Patent |
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The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors. The one or more processor subunits are configured to receive a sparse vector indicator from a host external to the at least one computational memory chip and, based on the received sparse vector indicator and the one or more portions of the embedding table, generate one or more vector sums.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230823&DB=EPODOC&CC=EP&NR=4229511A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230823&DB=EPODOC&CC=EP&NR=4229511A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DAYAN, Gal</creatorcontrib><creatorcontrib>MAYER-WOLF, Ilan</creatorcontrib><creatorcontrib>BETITO, Shai</creatorcontrib><creatorcontrib>ZEYDE, Roman</creatorcontrib><creatorcontrib>SRETER, Hillel</creatorcontrib><creatorcontrib>SPEKTOR, Evgeny</creatorcontrib><creatorcontrib>KOREN, Shay</creatorcontrib><creatorcontrib>HILLEL, Eliad</creatorcontrib><creatorcontrib>SITY, Elad</creatorcontrib><creatorcontrib>BRAUDO, Shany</creatorcontrib><title>MEMORY APPLIANCES FOR MEMORY INTENSIVE OPERATIONS</title><description>Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors. 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The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors. The one or more processor subunits are configured to receive a sparse vector indicator from a host external to the at least one computational memory chip and, based on the received sparse vector indicator and the one or more portions of the embedding table, generate one or more vector sums.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | MEMORY APPLIANCES FOR MEMORY INTENSIVE OPERATIONS |
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