PROCESSOR WITH MULTIPLE OP CACHE PIPELINES

A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache...

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Hauptverfasser:	COHEN, Robert B, KALAISELVAN, Sudherssen, MOSSMAN, James, BYBELL, Anthony J, LIN, Tzu-Wei
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	COHEN, Robert B KALAISELVAN, Sudherssen MOSSMAN, James BYBELL, Anthony J LIN, Tzu-Wei
description	A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.
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title	PROCESSOR WITH MULTIPLE OP CACHE PIPELINES
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