CIRCUIT TECHNIQUES FOR ENHANCED ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS
Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor)....
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | eng ; fre ; ger |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | CHILLARA, Krishna Chaitanya JALILIZEINALI, Reza DUNDIGAL, Sreeker CHEN, Wen-Yi |
description | Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP4173043A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP4173043A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP4173043A13</originalsourceid><addsrcrecordid>eNqNyrEKwjAQBuAuDqK-w406CJYUnOPlrwlIornLXIrESbRQ3x8XH8DpW75l4zlkLkFJwT6GW4FQnzIhehsZjnABa06iVgOTC8Le5jNoC3E7yulURCNE1s3iMT7nuvm5aqiHst_X6T3UeRrv9VU_A65dezSHztjW_FG-tG0scQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CIRCUIT TECHNIQUES FOR ENHANCED ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS</title><source>esp@cenet</source><creator>CHILLARA, Krishna Chaitanya ; JALILIZEINALI, Reza ; DUNDIGAL, Sreeker ; CHEN, Wen-Yi</creator><creatorcontrib>CHILLARA, Krishna Chaitanya ; JALILIZEINALI, Reza ; DUNDIGAL, Sreeker ; CHEN, Wen-Yi</creatorcontrib><description>Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS ; GENERATION ; PULSE TECHNIQUE ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230503&DB=EPODOC&CC=EP&NR=4173043A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230503&DB=EPODOC&CC=EP&NR=4173043A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHILLARA, Krishna Chaitanya</creatorcontrib><creatorcontrib>JALILIZEINALI, Reza</creatorcontrib><creatorcontrib>DUNDIGAL, Sreeker</creatorcontrib><creatorcontrib>CHEN, Wen-Yi</creatorcontrib><title>CIRCUIT TECHNIQUES FOR ENHANCED ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS</title><description>Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS</subject><subject>GENERATION</subject><subject>PULSE TECHNIQUE</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQBuAuDqK-w406CJYUnOPlrwlIornLXIrESbRQ3x8XH8DpW75l4zlkLkFJwT6GW4FQnzIhehsZjnABa06iVgOTC8Le5jNoC3E7yulURCNE1s3iMT7nuvm5aqiHst_X6T3UeRrv9VU_A65dezSHztjW_FG-tG0scQ</recordid><startdate>20230503</startdate><enddate>20230503</enddate><creator>CHILLARA, Krishna Chaitanya</creator><creator>JALILIZEINALI, Reza</creator><creator>DUNDIGAL, Sreeker</creator><creator>CHEN, Wen-Yi</creator><scope>EVB</scope></search><sort><creationdate>20230503</creationdate><title>CIRCUIT TECHNIQUES FOR ENHANCED ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS</title><author>CHILLARA, Krishna Chaitanya ; JALILIZEINALI, Reza ; DUNDIGAL, Sreeker ; CHEN, Wen-Yi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4173043A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS</topic><topic>GENERATION</topic><topic>PULSE TECHNIQUE</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHILLARA, Krishna Chaitanya</creatorcontrib><creatorcontrib>JALILIZEINALI, Reza</creatorcontrib><creatorcontrib>DUNDIGAL, Sreeker</creatorcontrib><creatorcontrib>CHEN, Wen-Yi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHILLARA, Krishna Chaitanya</au><au>JALILIZEINALI, Reza</au><au>DUNDIGAL, Sreeker</au><au>CHEN, Wen-Yi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CIRCUIT TECHNIQUES FOR ENHANCED ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS</title><date>2023-05-03</date><risdate>2023</risdate><abstract>Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng ; fre ; ger |
recordid | cdi_epo_espacenet_EP4173043A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS GENERATION PULSE TECHNIQUE SEMICONDUCTOR DEVICES |
title | CIRCUIT TECHNIQUES FOR ENHANCED ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T04%3A58%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHILLARA,%20Krishna%20Chaitanya&rft.date=2023-05-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP4173043A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |