GATE-TO-GATE ISOLATION FOR STACKED TRANSISTOR ARCHITECTURE VIA NON-SELECTIVE DIELECTRIC DEPOSITION STRUCTURE

An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) (101a) and a second semiconductor body (e.g., set of one or more nanoribbons) (101a) above the first semiconductor body. The first and second semiconduc...

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Bibliographische Detailangaben

Hauptverfasser:	RADOSAVLJEVIC, Marko, THOMAS, Nicole
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
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