HYBRID ANALOG/DIGITAL EQUALIZER ARCHITECTURE FOR HIGH-SPEED RECEIVER
Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the...
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| creator | Raviprakash, Karthik Alnabulsi, Basel Forey, Simon Reyes, Benjamin T Prabha, Praveen Wang, Luke Dellaire, Stephane Smith, Benjamin |
| description | Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels. |
| format | Patent |
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The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | HYBRID ANALOG/DIGITAL EQUALIZER ARCHITECTURE FOR HIGH-SPEED RECEIVER |
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