64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE
An apparatus to facilitate 64-bit two-dimensional (2D) block load with transpose is disclosed. The apparatus includes a processor comprising processing resources; and load store pipeline hardware circuitry coupled to the processing resources, the load store pipeline hardware circuitry to receive a 6...
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| creator | Shinde, Prathamesh Rhee, Changwon Ray, Joydeep Fu, FangWen Jiang, Hong Pal, Supratim Ashbaugh, Ben J |
| description | An apparatus to facilitate 64-bit two-dimensional (2D) block load with transpose is disclosed. The apparatus includes a processor comprising processing resources; and load store pipeline hardware circuitry coupled to the processing resources, the load store pipeline hardware circuitry to receive a 64-bit two-dimensional (2D) block load message with transpose from the processing resources. The load store pipeline hardware circuitry comprising a load store pipeline sequencer to map rows of a block of memory corresponding to the 64-bit 2D block load message with transpose to 64-bit standard load messages; and load store pipeline return circuitry to: sequentially number general register files (GRFs) used for returning elements of the block of memory accessed by the 64-bit standard load messages to the processing resources; and return, to the processing resources, the sequentially numbered GRFs in response to the 64-bit 2D block load message with transpose. |
| format | Patent |
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The apparatus includes a processor comprising processing resources; and load store pipeline hardware circuitry coupled to the processing resources, the load store pipeline hardware circuitry to receive a 64-bit two-dimensional (2D) block load message with transpose from the processing resources. The load store pipeline hardware circuitry comprising a load store pipeline sequencer to map rows of a block of memory corresponding to the 64-bit 2D block load message with transpose to 64-bit standard load messages; and load store pipeline return circuitry to: sequentially number general register files (GRFs) used for returning elements of the block of memory accessed by the 64-bit standard load messages to the processing resources; and return, to the processing resources, the sequentially numbered GRFs in response to the 64-bit 2D block load message with transpose.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ; PHYSICS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221228&DB=EPODOC&CC=EP&NR=4109386A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221228&DB=EPODOC&CC=EP&NR=4109386A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Shinde, Prathamesh</creatorcontrib><creatorcontrib>Rhee, Changwon</creatorcontrib><creatorcontrib>Ray, Joydeep</creatorcontrib><creatorcontrib>Fu, FangWen</creatorcontrib><creatorcontrib>Jiang, Hong</creatorcontrib><creatorcontrib>Pal, Supratim</creatorcontrib><creatorcontrib>Ashbaugh, Ben J</creatorcontrib><title>64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE</title><description>An apparatus to facilitate 64-bit two-dimensional (2D) block load with transpose is disclosed. The apparatus includes a processor comprising processing resources; and load store pipeline hardware circuitry coupled to the processing resources, the load store pipeline hardware circuitry to receive a 64-bit two-dimensional (2D) block load message with transpose from the processing resources. The load store pipeline hardware circuitry comprising a load store pipeline sequencer to map rows of a block of memory corresponding to the 64-bit 2D block load message with transpose to 64-bit standard load messages; and load store pipeline return circuitry to: sequentially number general register files (GRFs) used for returning elements of the block of memory accessed by the 64-bit standard load messages to the processing resources; and return, to the processing resources, the sequentially numbered GRFs in response to the 64-bit 2D block load message with transpose.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAwM9F18gxRCAn313Xx9HX1C_b093P0UXDy8Xf2VvDxd3RRCPcM8VAICXL0Cw7wD3blYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgEmhgaWxhZmjobGRCgBAMWBJbM</recordid><startdate>20221228</startdate><enddate>20221228</enddate><creator>Shinde, Prathamesh</creator><creator>Rhee, Changwon</creator><creator>Ray, Joydeep</creator><creator>Fu, FangWen</creator><creator>Jiang, Hong</creator><creator>Pal, Supratim</creator><creator>Ashbaugh, Ben J</creator><scope>EVB</scope></search><sort><creationdate>20221228</creationdate><title>64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE</title><author>Shinde, Prathamesh ; Rhee, Changwon ; Ray, Joydeep ; Fu, FangWen ; Jiang, Hong ; Pal, Supratim ; Ashbaugh, Ben J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP4109386A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Shinde, Prathamesh</creatorcontrib><creatorcontrib>Rhee, Changwon</creatorcontrib><creatorcontrib>Ray, Joydeep</creatorcontrib><creatorcontrib>Fu, FangWen</creatorcontrib><creatorcontrib>Jiang, Hong</creatorcontrib><creatorcontrib>Pal, Supratim</creatorcontrib><creatorcontrib>Ashbaugh, Ben J</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shinde, Prathamesh</au><au>Rhee, Changwon</au><au>Ray, Joydeep</au><au>Fu, FangWen</au><au>Jiang, Hong</au><au>Pal, Supratim</au><au>Ashbaugh, Ben J</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE</title><date>2022-12-28</date><risdate>2022</risdate><abstract>An apparatus to facilitate 64-bit two-dimensional (2D) block load with transpose is disclosed. The apparatus includes a processor comprising processing resources; and load store pipeline hardware circuitry coupled to the processing resources, the load store pipeline hardware circuitry to receive a 64-bit two-dimensional (2D) block load message with transpose from the processing resources. The load store pipeline hardware circuitry comprising a load store pipeline sequencer to map rows of a block of memory corresponding to the 64-bit 2D block load message with transpose to 64-bit standard load messages; and load store pipeline return circuitry to: sequentially number general register files (GRFs) used for returning elements of the block of memory accessed by the 64-bit standard load messages to the processing resources; and return, to the processing resources, the sequentially numbered GRFs in response to the 64-bit 2D block load message with transpose.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre ; ger |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS |
| title | 64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE |
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