SYNCRONIZATION OF INTERRUPT PROCESSING TO REDUCE POWER CONSUMPTION

The present disclosure provides a processor comprising at least one core including a first core, an interrupt controller and interrupt delay logic to: receive a first interrupt at a first time; delay the first interrupt from being processed by a first time delay that begins at the first time unless the first interrupt is pending at a second time when a second interrupt is processed by the first core; and if the first interrupt is pending at the second time, indicate to the first core to begin to process the first interrupt prior to completion of the first time delay, wherein the second interrupt is received periodically. The interrupt delay logic is further to: receive a third interrupt at a third time and assign to the third interrupt a second time delay, delay processing of the third interrupt from the third time by the second time delay unless the third interrupt is pending while the first interrupt or the second interrupt are being processed; if the third interrupt is pending while the first interrupt or the second interrupt is being processed, indicate to the first core to process the third interrupt without completion of the second time delay; if the third interrupt is not pending while the first interrupt is to be processed, the interrupt delay logic is to indicate to the core to process the third interrupt after completion of the second time delay.