ARBITRATION SCHEME FOR COHERENT AND NON-COHERENT MEMORY REQUESTS

A processor in a system is responsive to a coherent memory request buffer having a plurality of entries to store coherent memory requests from a client module and a non-coherent memory request buffer having a plurality of entries to store non-coherent memory requests from the client module. The clie...

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Bibliographische Detailangaben

Hauptverfasser:	BRANOVER, Alexander J, TSIEN, Benjamin, ARORA, Sonu
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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