METHOD FOR DATA SYNCHRONIZATION BETWEEN HOST END AND FPGA ACCELERATOR

Disclosed are a method for data synchronization between a host side and a Field Programmable Gate Array (FPGA) accelerator, a Bidirectional Memory Synchronize Engine (DMSE), a FPGA accelerator, and a data synchronization system. The method includes: in response to detection of data migration from a host side to a preset memory space, generating second state information according to first state information in a first address space, and writing the second state information to a second address space (S201); and in response to detection of the second state information in the second address space, calling Direct Memory Access (DMA) to migrate data in the preset memory space to a memory space of a FPGA accelerator, and copying the second state information to the first address space, so as to implement synchronization (S202). It can be seen that, according to the method, a data synchronization operation is implemented based on state information in two address spaces, and double-end memory data synchronization is performed by a controller at the side of the FPGA accelerator. Therefore, the data synchronization latency is reduced, and the system throughput is improved.